地址到物理地址的转换逻辑 [英] The translation logic of the address to physical address

问题描述

英特尔80X86架构提供分段内存模型，PC内存可视化为分段集合，每个段长64 KB，长度为16，地址为16的倍数。

这意味着第一个地址（0000h），第二地址（0010h），....等。

为什么每个地址的多个16 ?? !!

当第一段：0000，并且最后地址是（ffffh）

i认为下一个地址（ffffh）（段＃2的地址）等于（10000h）!!!!!!

解决方案

请参阅我对该问题的评论。此寻址模型仅适用于x86的实模式，并且非常简单： http://en.wikipedia.org/wiki/X86_memory_segmentation [ ^ ]。



在80286中，特别是在80386中，还有更多。







让我们看看。想象一下你要为CPU设计寻址，但是已经做出了一些主要决定，并且决定所有寄存器都是8位或16位，系统地址总线只有20位（处理不超过1M的内存） ）。这些是最基本的硬件限制，它们是给出的;并且假设您需要定义更多细节，指令集。



你如何处理内存？一个16位寄存器是不够的，两个寄存器会产生32位，太多了。它已经告诉我们段：偏移地址必须在物理上可用时产生更大的地址空间。它表示两个选项之一：段中的某些值：偏移空间应视为无效，或者单个物理地址可用不同的段：偏移对表示。很明显，第二种解决方案更好一些。大多数内存对象可以被64K限制（一个16位寄存器可以寻址64K），因此我们可以以地址的形式传递对象的地址：偏移一次，内部仅使用偏移量运行。



让我们从段开始吧。正如文章中所解释的那样，16位段选择器被解释为线性20位地址的最高16位。



让我们看看它是如何以十六进制形式显示的，这是最简单的。一个十六进制数字代表4位。如果您的地址为1234：0000，则将其转换为物理地址12340（4位的5位数使得20位）。偏移部分只是添加和偏移到物理地址。假设有些地址加载到DS：DX寄存器中。物理地址计算为（DS <4）+ DX。对于ABCD：0000示例，它将是

 DS：ABCD 
（DS << 4）：12340 
物理地址： 12340 + 0。

在DX中输入不同的值，你将得到12340到12340 + FFFF之间的地址范围。



现在你可以看重叠。让我们考虑最近段的物理地址范围，段移动16（4位移位），但段的大小是64K：

 1234：0000。 1234：FFFF表示12340 .. 2233F 
 1235：0000 .. 1235：FFFF表示12350 .. 2234F 
 1236：0000 .. 1236：FFFF表示12350 .. 2235F 
 ...等等，增量为16 

同样的事情，甚至更简单：假设您的20位地址空间被标记细分，从零开始，它们之间的距离为16字节。它们可以从0到FFFF枚举。现在，在CPU地址段：偏移量中，段表示此标记的数量，偏移量表示从该标记开始的字节偏移量。



请注意在PC中基于8086/8088（PC XT）的电路板架构，只有640K的内存可以物理安装和访问。后来，当80286 CPU到货时，较新的架构PC AT引入了几乎从未实际使用过的有点蹩脚的保护模式。即使这样的PC允许一些Megs的内存，实模式也不允许甚至是第一个1M的寻址，它仍然是640K（使用一些肮脏的技巧可以访问完整的兆字节）。我遇到了许多傻瓜，他们购买的兆字节非常自豪，他们从未明白他们的系统没有使用它们。没有一个普遍好的系统在保护模式下工作（我不算所谓的DOS扩展器，这也不常见）。只有i386终于打破了局面。

-SA

the intel 80X86 architecture provide segmented memory model ,the PC memory is visualized as collection of segmented ,each segment 64 KByte long .start on a address that is multiple of 16.
this mean First address (0000h) ,second address (0010h),....etc.
why each address multiple of 16 ??!!
when first segment: 0000, and last address is (ffffh)
i think the next address after (ffffh) (The address of segment #2) equal (10000h) !!!!!!

解决方案

Please see my comment to the question. This addressing model is only for real mode of x86, and is extremely simple: http://en.wikipedia.org/wiki/X86_memory_segmentation[^].

In both 80286 and especially in 80386, there is a lot more.

[EDIT #1]

Let's see. Imagine you about to design addressing for a CPU, but some main decisions are already made, and it is decided that all registers will be 8 or 16 bits, and the system address bus is only 20 bits (to address no more than 1M of memory). Those are most basic hardware limitations, they are given; and let's say you need to define further detail, the instruction set.

How would you address the memory? One 16-bit register is not enough, two registers would make 32-bits, way too many. It already tells us that segment:offset address would have to make bigger address space then physically available. It means one of the two options: either some of the values in segment:offset space should be considered invalid, or a single physical address could be represented with different segment:offset pairs. It's pretty obvious that the second solution is somewhat better. Most memory objects could be limited by 64K (one 16-bit register can address 64K), so we can pass the address of object in the form of address:offset just once, and internally operate only with offsets.

Let's start with segment. As it is explained in the article, " the 16-bit segment selector is interpreted as the most significant 16 bits of a linear 20-bit address".

Let's see how it looks in hexadecimal form, which is the easiest. One hexadecimal digits represent 4 bits. If you have the address 1234:0000, it is translated to the physical address of 12340 (5 digits of 4 bit make 20 bits). And the offset part simply add and offset to the physical address. Let's say, some address is loaded in DS:DX registers. The physical address is calculated as (DS << 4) + DX. For the ABCD:0000 example, it would be

DS: ABCD
(DS << 4):  12340
physical address: 12340 + 0.

Put different values in DX, and you will get the address range between 12340 to 12340 + FFFF.

Now you can see overlapping. Let's consider the range of physical addresses for closest segments, segments are shifted by 16 (4 bit shift), but the size of segments is 64K:

1234:0000 .. 1234:FFFF means 12340 .. 2233F
1235:0000 .. 1235:FFFF means 12350 .. 2234F
1236:0000 .. 1236:FFFF means 12350 .. 2235F
...and so on, with the increment of 16

[EDIT #2]

Same thing, even simpler: imagine that your 20-bit address space is subdivided by "marks", positioned from zero, with 16-byte distance between them. They can be enumerated from 0 to FFFF. Now, in the CPU address segment:offset, the segment means the number of such mark, and offset means the offset in bytes from this mark.

Note that in PC board architectures based on 8086/8088 ("PC XT"), only 640K of memory was physically installable and accessible. Later, when 80286 CPUs arrived, newer architecture "PC AT" introduced somewhat lame version of protected mode which almost never was practically used. Even though such PCs allowed some Megs of memory, real mode did not allow addressing even the first 1M, it remained 640K (with the full megabyte accessible with some dirty tricks). I met a number of morons very proud of megabytes they purchased who never understood that their systems did not use them. There was no a widespread good system working in protection mode (I don't count so called "DOS extenders" which also were not common). Only i386 finally broke the ice.

—SA

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