什么时候应该使用reg代替wire? [英] When should I use reg instead of wire?

问题描述

当我做作业时，我对reg和wire感到困惑.我不明白REG和电线恰好之间的差异.您能尽快解释一下吗?另外，我不知道，当我使用而不是?

I'm confused about reg and wire when I was doing my homework. I could not understand differences between reg and wire exactly. Can you explain shortly? Also, I wonder that what will happen when I use output q instead of output reg q?

推荐答案

在模拟中，Verilog wire的行为类似于金属，轨道，电线，而Verilog 是一个变量，它是存储*.

In simulation, a Verilog wire behaves like a piece of metal, a track, a wire, whilst a Verilog reg is a variable, it is storage*.

在模拟它们之间的差异可以通过示出，如果我从一个以上的地方分配给他们会发生什么情况示出.如果我分配给从一个以上的地方，仿真的行为完全我仿佛这两个导线短路在一起.所以，

The difference between them in simulation can be illustrated by showing what happens if I assign to them from more than one place. If I assign to a wire from more than one place, the simulation will behave exactly as if I had shorted those two wires together. So,

wire w;
assign w = 1'b1;
assign w = 1'b0;
initial
   $display("w= %b", w);

将显示x.的的值将是因为一个正在驾驶和其他和因此这将决心到.通过这种方式，它对真实硬件的行为进行建模，其中x表示 unknown 值(一个驱动器高而另一个驱动器低的实际线驱动器的值实际上是未知的)

will display x. The value of w will be x because one assign is driving 1'b1 and the other 1'b0 and so this will resolve to an x. In this way it is modelling the behavoiur of real hardware, where x represents an unknown value (the value of a real piece of wire drive high by one driver and low by another will really be unknown).

如果我从多个地方为reg(一个变量)赋值，我会得到不同的行为.代替的解决的一个的将只是采取任何值最后分配.所以，

If I assign to a reg - a variable - from more than one place, I will get different behaviour. Instead of resolving to an x, the reg will just take whatever value is assigned last. So,

reg r;

initial
  r = 1'b1;

initial
  r = 1'b0;

initial
   #1 $display("r= %b", r);

将显示任一或这取决于初始块执行最后一个(一些不确定性的).

will display either 1 or 0 depending on which initial block is executed last (something that is not deterministic).

注意，该从块驱动. A 必须从一个或块驱动(所谓的程序代码).假设您正在编写Verilog，而不是System Verilog，则无法从assign语句或实例化模块的输出分配给reg.因此，如果您要分配给从程序代码的东西，你必须使用;如果要分配assign语句或实例化模块的输出中的某些内容，则必须为wire..因此，可以确定是否将output定义为或完全取决于你分配给它的位置.如果从一个块分配给它，它必须是一个;如果你从一个语句或实例化的模块的输出分配给它，它必须是一个

Notice, that the reg is driven from initial blocks. A reg has to be driven from an initial or an always block (so-called procedural code). Assuming you are writing Verilog, not System Verilog, you cannot assign to a reg from an assign statement nor from the output of an instantiated module. So, if you want to assign to something from procedural code, you have to use a reg; if you want to assign to something from an assign statement or the output of an instantiated module, it has to be a wire. And, therefore it follows that whether you define an output as a reg or a wire depends entirely on where you're assigning to it. If you're assigning to it from an always block, it needs to be a reg; if you're assigning to it from an assign statement or the output of an instantiated module, it needs to be a wire.

这是在一个和在仿真的行为的差异.您的合成器将对reg进行不同的解释.如果从多个always块中分配一个reg(不能合成initial块)，则逻辑合成器将合成两个硬件来驱动同一块金属，轨道，导线等-您可能不想要的东西.

That is the difference in the behaviour of a reg and a wire in simulation. Your synthesiser, will interpret a reg differently. If you assign to a reg from more than one always block (you can't synthesise initial blocks), then you logic synthesiser will synthesise two pieces of hardware driving the same piece of metal, track, wire, whatever - something you probably don't want.

*即不指将必然成为存储(即，触发器)中合成时.是否一个`REG变为触发器或组合逻辑取决于它是否在一个或sequential-组合风格的分配总是阻塞.

*That does not mean a reg will necessarily become storage (ie a flip-flop) when synthesised. Whether, a `reg becomes a flip-flop or combinational logic depends on whether it is assigned in a sequential- or combinational-style always block.

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