使用级联2位比较器实现2n位比较器 [英] Implementing a 2n-bit comparator using cascaded 2-bit comparators
问题描述
到目前为止，我已经将此代码用于2位比较器.
module twobitcomparator(xgtyin,xety,xltyin,x1,x0,y1,y0,xgty,xety,xlty);
//I/O
output xgty, xety, xlty; //xgty - x>y, xlty - x<y, xety - x=y
input x1, x0, y1, y0, xgtyin, xetyin, xltyin;
//specify circuit behavior
assign r = (xgyin);
assign s = (xlyin);
assign t = (xetyin);//not sure if I need an xetyin
assign a = (x1&~y1);
assign b = (x1&x0&~y0);
assign c = (x0&~y1&~y0);
assign xgty = (a|b|c|r);//X>Y
assign d = (~x0&~y0);
assign e = (x0&y0);
assign f = (x1&y1);
assign g = (~x1&~y1);
assign xety = ((d|e)&(f|g));//X=Y
assign h = (~x1&~x0&y0);
assign i = (~x1&y1);
assign j = (~x0&y1&y0);
assign xlty = (h|i|j|s);//X<Y
endmodule
这看起来不错吗?我为此编写了一个测试平台，并查看了wave，输出对于输入而言是正确的，但是我不确定这是否是最有效的方法.
对于级联，我知道最高位比较器的结果(如果是不等式)将只需要向下传递给其余比较器，这将是最终结果.如果它们相等，那么我只需要找到存在不等式的最高位比较器，就需要像我提到的那样将其级联.
我一直坚持让他们级联，对Verilog来说我是一个新手，我不知道如何将每个比较器的结果带入下一个比较器.这是我的尝试.
module ncompare#( parameter n = 2)(input [2*n-1:0] xgyin, xlyin,
input [2*n-1:0] x1, x0, y1, y0,
output [2*n-1:0] xgy, xey, xly,
output xqyout);
wire xqyin;
assign xqyin = 1'b0;
twobitcomparator s1(.xgyin(xgyin[xqyin]), .xlyin(xlyin[xqyin]),
.x1(x1[2*n-1]), .x0(x0[2*n-2]), .y1(y1[2*n-1]), .y0(y0[2*n-2]),
.xgy(xgy[ripple0]), .xey(xey[ripple1]), .xly(xly[ripple2]));
twobitcomparator s0(.xgyin(xgyin[ripple0]), .xlyin(xlyin[ripple2]),
.x1(x1[1]), .x0(x0[0]), .y1(y1[1]), .y0(y0[0]),
.xgy(xgy[ripple3]), .xey(xey[ripple4]), .xly(xly[ripple5]));
endmodule
我想我需要使用generate语句，因为我需要使它对任何参数n都起作用，但是我不知道如何使用generate，因为我查看的所有示例只有一个输出，而我只有三个输出(那个也是下一个比较器的输入！
感谢所有帮助！
2位比较器模块可以重写为
module twobitcomparator(xgtyin,xltyin,x,y,xgty,xlty,xety);
output xgty, xety, xlty;
input xgtyin, xltyin;
input [1:0] x,y;
assign xgty = xgtyin | (~xltyin & ((x[1] > y[1]) | ((x[1] == y[1]) & (x[0] > y[0]))));
assign xlty = xltyin | (~xgtyin & ((x[1] < y[1]) | ((x[1] == y[1]) & (x[0] < y[0]))));
assign xety = ~(xlty | xgty);
endmodule
我将两位输入视为总线，而不是将它们视为单个位(Verilog允许您执行此操作).我已经修剪掉了代码中存在的众多中间结果.这使代码更易于理解，因为您不必跟踪所有这些临时连接.
然后，我在EDA Playground上使用Icarus Verilog模拟了此模块.链接在这里 https://www.edaplayground.com/x/5KRL
使用这两个位比较器的四位比较器可以编写如下.
module fourbitcomparator(xgtyin,xltyin,x,y,xgty,xlty,xety);
output xgty, xety, xlty;
input xgtyin, xltyin;
input [3:0] x,y;
wire xgty_1,xlty_1,xety_1;
twobitcomparator u_1 (
.xgtyin(xgtyin),
.xltyin(xltyin),
.x(x[3:2]),
.y(y[3:2]),
.xgty(xgty_1),
.xlty(xlty_1),
.xety(xety_1)
);
twobitcomparator u_0 (
.xgtyin(xgty_1),
.xltyin(xlty_1),
.x(x[1:0]),
.y(y[1:0]),
.xgty(xgty),
.xlty(xlty),
.xety(xety)
);
endmodule
最后使用2位比较器的2n位比较器可以概括如下
module twoN_bitcomparator #(
parameter N = 2
)(
input xgtyin,
input xltyin,
input [(2*N-1):0]x,
input [(2*N-1):0]y,
output xgty,
output xlty,
output xety
);
wire [N:0] xgty_w,xlty_w,xety_w;
assign xgty_w[N] = xgtyin;
assign xlty_w[N] = xltyin;
generate
genvar i;
for (i=0;i<=(N-1);i=i+1)
begin:TWOBITGEN
twobitcomparator u_1 (
.xgtyin(xgty_w[i+1]),
.xltyin(xlty_w[i+1]),
.x(x[(2*i+1) : (2*i)]),
.y(y[(2*i+1) : (2*i)]),
.xgty(xgty_w[i]),
.xlty(xlty_w[i]),
.xety(xety_w[i])
);
end
endgenerate
assign xgty = xgty_w[0];
assign xlty = xlty_w[0];
assign xety = xety_w[0];
endmodule
也可以在EDA游乐场的 https://www.edaplayground.com上获得此通用模块的模拟. /x/2fbr 小型测试平台的波形也可从 https://www.edaplayground.com/w/x获得. /27X
So far I have this code for a 2-bit comparator.
module twobitcomparator(xgtyin,xety,xltyin,x1,x0,y1,y0,xgty,xety,xlty);
//I/O
output xgty, xety, xlty; //xgty - x>y, xlty - x<y, xety - x=y
input x1, x0, y1, y0, xgtyin, xetyin, xltyin;
//specify circuit behavior
assign r = (xgyin);
assign s = (xlyin);
assign t = (xetyin);//not sure if I need an xetyin
assign a = (x1&~y1);
assign b = (x1&x0&~y0);
assign c = (x0&~y1&~y0);
assign xgty = (a|b|c|r);//X>Y
assign d = (~x0&~y0);
assign e = (x0&y0);
assign f = (x1&y1);
assign g = (~x1&~y1);
assign xety = ((d|e)&(f|g));//X=Y
assign h = (~x1&~x0&y0);
assign i = (~x1&y1);
assign j = (~x0&y1&y0);
assign xlty = (h|i|j|s);//X<Y
endmodule
Does this look good? I wrote a testbench for it and looked at the wave and the outputs were correct for the inputs, but I'm not sure if it's the most efficient way.
For the cascading, I know that the highest bit comparator's result (if it is an inequality) will just need to be sent down through the rest of the comparators and that will be the final result. If they are equal, then I just have to find the highest bit comparator where there is an inequality and that needs to be cascaded like I mentioned.
I am stuck on getting them to cascade, I am very new to Verilog and I have no clue how I should get each comparator's result into the next one. Here is my attempt.
module ncompare#( parameter n = 2)(input [2*n-1:0] xgyin, xlyin,
input [2*n-1:0] x1, x0, y1, y0,
output [2*n-1:0] xgy, xey, xly,
output xqyout);
wire xqyin;
assign xqyin = 1'b0;
twobitcomparator s1(.xgyin(xgyin[xqyin]), .xlyin(xlyin[xqyin]),
.x1(x1[2*n-1]), .x0(x0[2*n-2]), .y1(y1[2*n-1]), .y0(y0[2*n-2]),
.xgy(xgy[ripple0]), .xey(xey[ripple1]), .xly(xly[ripple2]));
twobitcomparator s0(.xgyin(xgyin[ripple0]), .xlyin(xlyin[ripple2]),
.x1(x1[1]), .x0(x0[0]), .y1(y1[1]), .y0(y0[0]),
.xgy(xgy[ripple3]), .xey(xey[ripple4]), .xly(xly[ripple5]));
endmodule
I think I need to use a generate statement since I need to make it work for any parameter n but I have no clue how to use generate since all examples I've looked at only have one output and I have three (that are also the next comparator's inputs! Agh!)
Thanks for any and all help!
The 2-bit comparator module can be rewritten as
module twobitcomparator(xgtyin,xltyin,x,y,xgty,xlty,xety);
output xgty, xety, xlty;
input xgtyin, xltyin;
input [1:0] x,y;
assign xgty = xgtyin | (~xltyin & ((x[1] > y[1]) | ((x[1] == y[1]) & (x[0] > y[0]))));
assign xlty = xltyin | (~xgtyin & ((x[1] < y[1]) | ((x[1] == y[1]) & (x[0] < y[0]))));
assign xety = ~(xlty | xgty);
endmodule
I have treated the two bit input as a bus instead of treating them as individual bits (Verilog allows you to do that). I have trimmed out the numerous intermediate results that were present in your code. This makes the code easier to understand as you do not have to keep track of all those temporary wires.
I then simulated this module using Icarus Verilog on EDA Playground. The link is here https://www.edaplayground.com/x/5KRL
A four-bit comparator that uses these twobitcomparators can be written as follows.
module fourbitcomparator(xgtyin,xltyin,x,y,xgty,xlty,xety);
output xgty, xety, xlty;
input xgtyin, xltyin;
input [3:0] x,y;
wire xgty_1,xlty_1,xety_1;
twobitcomparator u_1 (
.xgtyin(xgtyin),
.xltyin(xltyin),
.x(x[3:2]),
.y(y[3:2]),
.xgty(xgty_1),
.xlty(xlty_1),
.xety(xety_1)
);
twobitcomparator u_0 (
.xgtyin(xgty_1),
.xltyin(xlty_1),
.x(x[1:0]),
.y(y[1:0]),
.xgty(xgty),
.xlty(xlty),
.xety(xety)
);
endmodule
Finally a 2n bit comparator using twobitcomparators, can be generalised as follows
module twoN_bitcomparator #(
parameter N = 2
)(
input xgtyin,
input xltyin,
input [(2*N-1):0]x,
input [(2*N-1):0]y,
output xgty,
output xlty,
output xety
);
wire [N:0] xgty_w,xlty_w,xety_w;
assign xgty_w[N] = xgtyin;
assign xlty_w[N] = xltyin;
generate
genvar i;
for (i=0;i<=(N-1);i=i+1)
begin:TWOBITGEN
twobitcomparator u_1 (
.xgtyin(xgty_w[i+1]),
.xltyin(xlty_w[i+1]),
.x(x[(2*i+1) : (2*i)]),
.y(y[(2*i+1) : (2*i)]),
.xgty(xgty_w[i]),
.xlty(xlty_w[i]),
.xety(xety_w[i])
);
end
endgenerate
assign xgty = xgty_w[0];
assign xlty = xlty_w[0];
assign xety = xety_w[0];
endmodule
The simulation of this generalised module is also available on EDA playground at https://www.edaplayground.com/x/2fbr The waveform for the small testbench is also available at https://www.edaplayground.com/w/x/27X
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