在VHDL中按位16位? [英] 16-bit bitwise and in VHDL?

问题描述

如果我需要对两个16位输入执行按位AND运算并在VHDL中获得16位输出，我是否能够对两个输入进行AND运算并将结果存储为输出矢量?还是我需要遍历输入的每一位，然后将它们与之相乘，然后将结果存储在输出向量中?像or和xor这样的操作是否会类似地工作?

If I needed to perform a bitwise AND operation of two 16bit inputs and obtain a 16bit output in VHDL, would I be able to just AND the two inputs and store the result as the output vector? Or would I need to loop through each bit of the inputs, AND them, then store the result in the output vector? Would this work similarly for operations like or and xor?

推荐答案

对于std_logic，std_ulogic，std_logic_vector和std_ulogic_vector(类型，std_logic_1164包中的和"运算符是重载的)通常使用).它也为bit和bit_vector(以及signed和unsigned)定义.

The "and" operator is overloaded in the std_logic_1164 package for std_logic, std_ulogic, std_logic_vector, and std_ulogic_vector (the types typically used). It is also defined for bit and bit_vector (as well as signed and unsigned).

因此，就像应用"and"运算符一样简单.例如:

So it is as straightforward as just applying the "and"operator. For example:

architecture rtl of test is
  signal a : std_logic_vector(15 downto 0);
  signal b : std_logic_vector(15 downto 0);
  signal y : std_logic_vector(15 downto 0);
begin
  y <= a and b; -- Or 'y <= a xor b;' or 'y <= a or b;', etc
end architecture rtl;

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