在gnu make中，静态模式规则中的前提条件可以有不同的后缀吗 [英] In gnu make, can the prerequisites in a static pattern rule have different suffixes

问题描述

我们的make文件使用如下静态模式规则编译.c源文件:

Our make file compiles .c source files with a static pattern rule like this:

OBJECTS = foo.o bar.o baz.o

$(OBJECTS): %.o: %.c
    $(CC) $< $(C_OPTIONS) -c -o $@

我需要将.c文件之一更改为Objective-C .m文件.对于两种源类型，调用编译器都是相同的，因此我想使用相同的规则，并对其进行调整以使其更加灵活.我宁愿不更改OPTIONS变量，因为它也用于链接步骤等.

I need to change one of the .c files to an Objective-C .m file. Invoking the compiler is the same for both source types, so I'd like to use the same rule and just tweak it to be more flexible. I'd rather not change the OPTIONS variable because it's also used for the linking step, etc.

是否有一种方法可以使上面的规则更加灵活，以同时容纳.c和.m文件?

Is there a way to make the rule above more flexible to accommodate both .c and .m files?

谢谢

推荐答案

我们可以将此或"行为添加到Make应该能够轻松完成的事情列表中，但事实并非如此.这是一种使用"eval"为每个对象创建单独规则的方法.

We can add this either-or behavior to the list of things Make should be able to do easily, but isn't. Here's a way to do it, using "eval" to create a seperate rule for each object.

define RULE_template
$(1): $(wildcard $(basename $(1)).[cm])
endef

OBJECTS = foo.o bar.o baz.o

$(foreach obj,$(OBJECTS),$(eval $(call RULE_template,$(obj))))

$(OBJECTS):
    $(CC) $< $(C_OPTIONS) -c -o $@ 

请注意，这取决于运行Make之前已经存在的源文件(foo.c或foo.m，但不能同时存在).如果您要在同一步骤中生成这些源，则将无法正常工作.

Note that this depends on the source files already existing before you run Make (foo.c or foo.m, but not both). If you're generating those sources in the same step, this won't work.

这是一种不太聪明，更可靠的方法.

CPP_OBJECTS = foo.o bar.o
OBJECTIVE_OBJECTS = baz.o
OBJECTS = $(CPP_OBJECTS) $(OBJECTIVE_OBJECTS)

$(CPP_OBJECTS): %.o: %.c 

$(OBJECTIVE_OBJECTS): %.o: %.m 

$(OBJECTS):
    $(CC) $< $(C_OPTIONS) -c -o $@ 

由于乔纳森·莱夫勒(Jonathan Leffler)，更正了对象分配.

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