在Makefile命令中声明的访问变量 [英] Access variable declared inside Makefile command

查看:130
本文介绍了在Makefile命令中声明的访问变量的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!

问题描述

我正在尝试访问由上一个命令声明的变量(在Makefile中).

I'm trying to access a variable declared by previous command (inside a Makefile).

这是Makefile:

all:
  ./script1.sh
  ./script2.sh

这是声明我要访问的变量的脚本,script1.sh:

Here's the script declaring the variable I want to access,script1.sh:

#!/usr/bin/env bash
myVar=1234

以下是脚本尝试访问先前定义的变量script2.sh:

Here's the script trying to access the variable previously defined, script2.sh:

#!/usr/bin/env bash
echo $myVar

不幸的是,当我运行make时,无法访问myVar.还有其他方法吗?谢谢.

Unfortunately when I run make, myVar isn't accessible. Is there an other way around? Thanks.

推荐答案

Make将在其自己的shell中运行每个shell命令.当外壳退出时,它的环境就会丢失.

Make will run each shell command in its own shell. And when the shell exits, its environment is lost.

如果您希望一个脚本中的变量在下一个脚本中可用,则可以使用一些结构来实现.例如:

If you want variables from one script to be available in the next, there are constructs which will do this. For example:

all:
    ( . ./script1.sh; ./script2.sh )

这会使Make启动一个shell来处理两个脚本.

This causes Make to launch a single shell to handle both scripts.

还请注意,您将需要 export 变量,以使其在第二个脚本中可见;未导出的变量仅适用于本地脚本,不适用于其启动的子外壳.

Note also that you will need to export the variable in order for it to be visible in the second script; unexported variables are available only to the local script, and not to subshells that it launches.

更新(根据Kusalananda的评论):

UPDATE (per Kusalananda's comment):

如果要让Shell命令填充MAKE变量而不是仅填充环境变量,则可能有一些选项取决于运行的Make版本.例如,在BSD make和GNU make中,可以使用变量赋值修饰符",包括(从BSD make手册页开始):

If you want your shell commands to populate MAKE variables instead of merely environment variables, you may have options that depend on the version of Make that you are running. For example, in BSD make and GNU make, you can use "variable assignment modifiers" including (from the BSD make man page):

 !=      Expand the value and pass it to the shell for execution and
         assign the result to the variable.  Any newlines in the result
         are replaced with spaces.

因此,使用BSD make和GNU make,您可以执行以下操作:

Thus, with BSD make and GNU make, you could do this:

$ cat Makefile

foo!=   . ./script1.sh; ./script2.sh

all:
    @echo "foo=${foo}"

$
$ cat script1.sh
export test=bar
$
$ cat script2.sh
#!/usr/bin/env bash

echo "$test"
$
$ make
foo=bar
$

请注意,script1.sh不包含任何shebang,因为它是来源,因此无论在什么情况下都在调用shell中运行.这使得shebang行仅仅是一个评论.如果您使用的是默认外壳程序为POSIX而不是bash的系统(例如Ubuntu,Solaris,FreeBSD等),则此操作仍将有效,因为POSIX外壳程序都应了解导出变量的概念.

Note that script1.sh does not include any shebang because it's being sourced, and is therefore running in the calling shell, whatever that is. That makes the shebang line merely a comment. If you're on a system where the default shell is POSIX but not bash (like Ubuntu, Solaris, FreeBSD, etc), this should still work because POSIX shells should all understand the concept of exporting variables.

这篇关于在Makefile命令中声明的访问变量的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

查看全文
登录 关闭
扫码关注1秒登录
发送“验证码”获取 | 15天全站免登陆