递归make:插入`$(MAKEFLAGS)`的正确方法 [英] Recursive make: correct way to insert `$(MAKEFLAGS)`
问题描述
如何使用$(MAKEFLAGS)
(或将命令行中定义的变量传递给sub-make的另一种方式),以支持同时使用make VAR=val
和make -args
从shell调用的方式?
How can I use $(MAKEFLAGS)
(or another way of passing variables defined on the command line to sub-make) in a way that supports invocation from shell with both make VAR=val
and make -args
?
我需要可配置子项目,但我讨厌自动工具,因此我为此使用了make变量.从shell调用:
I need my subprojects configurable, but I hate autotools, so I'm using make variables for this, e.g. invoking from shell:
$ make USE_SSE3=1
和USE_SSE3
需要应用于所有子makefile中的所有内部版本.
and USE_SSE3
needs to apply to all builds in all sub-makefiles.
手册指出:
如果您执行"make -ks",那么MAKEFLAGS将获得值"ks".
if you do ‘make -ks’ then MAKEFLAGS gets the value ‘ks’.
因此,我在我的Makefile中使用了-$(MAKEFLAGS)
(带破折号).
Therefore I'm using -$(MAKEFLAGS)
(with a dash prefix) in my Makefile.
但是,当使用不带标志的变量时,会扩展为无效参数.如果我运行:
However, that expands into invalid arguments when variables with no flags are used. If I run:
$ make FOO=bar
然后子商标将无效-FOO=bar
.没有破折号前缀变量定义的OTOH有效,但是make -s
等无效.
then sub-make gets invalid -FOO=bar
. OTOH without the dash prefix variable definitions work, then but make -s
, etc. don't.
是否存在使参数传递和单独的变量定义与子makefile一起使用的语法/变量/hack?
Is there a syntax/variable/hack that makes passing of arguments and lone variable definitions work with sub-makefiles?
旧版$(MKFLAGS)
没有奇怪的破折号前缀问题,但也不包含变量定义.我曾尝试用$(patsubst)
修复变量,但这只会通过修剪空格使情况变得更糟.
The legacy $(MKFLAGS)
doesn't have the weird dash prefix problem, but it doesn't include variable definitions either. I've tried fixing the variable with $(patsubst)
, but that only made things worse by trimming whitespace.
我需要该解决方案与Mac OS X Mavericks随附的过时的GNU Make 3.81兼容.
I need the solution to be compatible with the outdated GNU Make 3.81 shipped with Mac OS X Mavericks.
foo:
$(MAKE) -C subproject -$(MAKEFLAGS)
$ make foo -s # MAKEFLAGS = 's'
$ make foo BAR=baz # MAKEFLAGS = 'BAR=baz'
$ make foo -j8 # MAKEFLAGS = ' --job-server=…'
推荐答案
完全不应该设置MAKEFLAGS
.你为什么要您没有给出任何理由.
You shouldn't set MAKEFLAGS
at all. Why do you want to? You didn't give any reason to do so.
MAKEFLAGS
实际上是要作为内部实现,将参数从父品牌传递到子品牌.通常,它不希望由makefile进行修改.您唯一可以做的有用的事情就是添加新标志.
MAKEFLAGS
is intended, really, to be an internal implementation passing arguments from a parent make to a child make. It's not intended, generally, to be modified by a makefile. About the only thing you can usefully do to it is add new flags.
如果仅使用$(MAKE)
变量而不是对make
进行硬编码来运行递归make,那么它将正常工作:
If you just run the recursive make using the $(MAKE)
variable rather than hardcoding make
, it will Just Work:
recurse:
@$(MAKE) all FOO=bar
或其他.
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