覆盖makefile中的`CC`和`CXX`变量 [英] Overriding `CC` and `CXX` variables in makefiles

问题描述

我有一个包含通用设置的主文件，还有一个具有项目特定设置的子文件.

从其他有关覆盖Makefile中的覆盖变量的问题中，我了解到可以在我的母版中使用以下代码生成文件:

CC ?= avr-gcc
CXX ?= avr-g++

在子文件中，我使用 colorgcc 并覆盖以下变量:

CC ?= color-avr-gcc
CXX ?= color-avr-g++

一切正常.

但是，如果我从子Makefile中删除了以上几行，则使用gcc和g++而不是avr-gcc和avr-g++来开始make.

我想CC和CXX的处理方式有所不同，make为它们提供了默认值，而我无法使用以下语句为它们分配默认值:

CC ?= avr-gcc
CXX ?= avr-g++

我的问题:

• 我的假设正确吗?
• 如果是，是否有其他方法可以提供默认值给主makefile中的CC和CXX，并允许使用它(如果我没有在子makefile中覆盖它们的话)?

修改:

根据 Chrono Kitsune 的建议，我做了以下

主生成文件

CC = avr-gcc
CXX = avr-g++
# Add other master macros here.
# Add other master targets here.

子生成文件

CC ?= color-avr-gcc
CXX ?= color-avr-g++
# There are no child macros or targets

include master.mk

不幸的是，即使这样也没有用.当我运行make child.mk时，它将拾取主版中定义的CC和CXX.

PS:顺便说一句，我的主makefile是Arduino的makefile，完整的源代码可在解决方案

使用起源函数，我终于可以使用以下组合了.

主生成文件

CC = avr-gcc
CXX = avr-g++
# Add other master macros here.
# Add other master targets here.

子Makefile

include master.mk

CC = color-avr-gcc
CXX = color-avr-g++
# There are no child macros or targets

现在，当我执行make child.mk时，它会拾取color-avr-gcc.如果我在子Makefile中对其进行注释，则它将使用主Makefile中的avr-gcc.

I have a master makefile, which contains generic settings, and a child makefile that has project specific settings.

From my other question about overriding variables in a makefile, I learned that I can use the following code in my master makefile:

CC ?= avr-gcc
CXX ?= avr-g++

In the child makefile, I use colorgcc and override these variables:

CC ?= color-avr-gcc
CXX ?= color-avr-g++

Everything works.

But, if I remove the above lines from my child makefile, make starts using gcc and g++ instead of avr-gcc and avr-g++.

I guess both CC and CXX are treated differently and they are provided with default values by make and I am not able to assign default values to them using the following statements:

CC ?= avr-gcc
CXX ?= avr-g++

My questions:

• Is my assumption correct?
• If yes, is there any other way to provide default values to CC and CXX in the master makefile and let make use it, if I don't override them in the child makefile?

Edit:

As per Chrono Kitsune's suggestion I did the following

master makefile

CC = avr-gcc
CXX = avr-g++
# Add other master macros here.
# Add other master targets here.

child makefile

CC ?= color-avr-gcc
CXX ?= color-avr-g++
# There are no child macros or targets

include master.mk

Unfortunately, even this didn't work. When I run make child.mk it is picking up the CC and CXX defined in master.

PS: BTW, my master makefile is a makefile for Arduino and the full source code is available in github.

解决方案

After debugging it using the origin function, I finally made to work with the following combination.

Master makefile

CC = avr-gcc
CXX = avr-g++
# Add other master macros here.
# Add other master targets here.

Child makefile

include master.mk

CC = color-avr-gcc
CXX = color-avr-g++
# There are no child macros or targets

Now when I do make child.mk it picks up color-avr-gcc. And if I comment it in child makefile, then it uses avr-gcc from master makefile.

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