GNU将变量“意外令牌"设为“ [英] GNU Make variable "unexpected token"

问题描述

我正在为一个FPGA团队开发一个makefile环境，而我目前在宏方面遇到了问题.我已经为TOOL_EXEC变量显示了它的定义，但是却出现了与双引号和括号相关的意外令牌"错误.如果我在双引号中加上双引号，则变量会在没有任何引号的情况下膨胀，并且不会产生任何错误，但是我们的工具要求将它们括在括号中.我需要传递全引号的括号信息，但是宏定义给我带来了问题！

I'm working on a makefile environment for an FPGA team and I'm currently having issues with a macro. I have it defined as shown for the TOOL_EXEC variable, but I'm getting an "unexpected token" error related to the double quotes and parenthesis. If I put double double quotes the variable inflates without any quotations at all and yields no error, however our tool requires them to be in parenthesis. I need to pass the fully quoted parenthesis information, but the macro definition is giving me issues!

语法错误出现在意外标记`('"

"syntax error near unexpected token `(' "

    Example call to tool: (This works fine)
    $ Tool --v v4.5 -odir . -verilog -vh "('name', 'propname', 'address', 'desc')" filename.rdl

    Desired Macro/variable: (not working)
    TOOL_EXEC = -odir . -verilog -vh "('name', 'propname', 'address', 'desc')"

有什么想法吗? 谢谢

推荐答案

只需使用反斜杠转义每个特殊字符(例如，引号，双引号或括号):

Just escape every special character (e.g. quote, double quote or parenthesis) with a backslash:

TOOL_EXEC = -odir . -verilog -vh \"\(\'name\', \'propname\', \'address\', \'desc\'\)\"

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