VHDL位向量运算符 [英] VHDL Bit Vector Operators

问题描述

在VHDL中完成一些简单的数学运算会遇到很多麻烦.我的语言太糟糕了，所以如果我的语法很愚蠢，我有一个借口:P.我正在尝试实现一个非常简单的随机数生成器，该生成器通过以下公式来计算伪随机数:

I'm having a lot of trouble getting some simple math done in VHDL. I'm terrible at this language so if my syntax is stupid or something, I have an excuse :P. I'm trying to implement a very simple random number generator that calculates a pseudo-random number by this formula:

种子=(种子* 1103515245)+ 12345

seed = (seed*1103515245) + 12345

我要如何做到:

这里的信号

signal seed: std_logic_vector(31 downto 0) := x"2B4C96B9";
signal multiply: std_logic_vector(31 downto 0) := x"41C64E6D";
signal add: std_logic_vector(31 downto 0) := x"00003039";
signal temp1: std_logic_vector(63 downto 0);
signal temp2: std_logic_vector(31 downto 0);

此处计算(在状态机中的状态下完成)

Computation here (done in a state in a state machine)

temp2 <= seed;
temp1 <= std_logic_vector((unsigned(temp2)*unsigned(multiply)));
seed <= std_logic_vector(unsigned(temp1(31 downto 0)) + unsigned(add));

temp2总是以未定义结尾.另外，种子最终也将变得不确定.我已经尝试了几种不同的方法，但是所有这些方法都是错误的，主要是因为向量的大小，顺序或操作.根据我通过半广泛使用的Google搜索发现的内容，我觉得目前正在做的很好，但我只是想不通.

temp2 always ends up being undefined. Additionally, seed ends up being undefined as well. I've tried it several different ways but all of them were wrong mostly because of the vector sizes and order or operations. I feel like I'm doing it right at the moment based on what I've found through semi-extensive Googling but I just can't figure it out.

我现在能想到的最好的事情是在状态机中以自己的状态执行计算的每个步骤.有人可以在这里看到我在做什么错吗?

The best thing I can think of right now is to do each step of the calculation in its own state in a state machine. Can anyone see what I'm doing wrong here?

推荐答案

VHDL与其他语言的不同之处在于，由<=分配的信号要等到delta延迟后才生效，因此无法读取. >

VHDL is different from other languages in that signal assign by <= does not take effect for read until after a delta delay, thus if you do:

temp2 <= seed;
temp1 <= std_logic_vector((unsigned(temp2)*unsigned(multiply)));
seed <= std_logic_vector(unsigned(temp1(31 downto 0)) + unsigned(add));

然后，在经过增量延迟之前，temp2实际上不会在用于分配temp1的表达式中进行读取更新.

then the temp2 not actually updated for read in the expression used to assign temp1 until a delta delay has passed.

根据有关设计的详细信息，可以考虑将中间变量声明为变量:

Depending on the details about your design, you can consider declaring the intermediate variables as variables:

variable temp1: std_logic_vector(63 downto 0);
variable temp2: std_logic_vector(31 downto 0);

，然后像这样分配:

temp2 := seed;
temp1 := std_logic_vector((unsigned(temp2)*unsigned(multiply)));
seed <= std_logic_vector(unsigned(temp1(31 downto 0)) + unsigned(add));

在这种情况下，中间变量temp1和temp2将在赋值后立即读取结果，而seed将在增量延迟后获得值，假设您不执行下一个迭代直到下一个周期.

In this case the intermediate variables temp1 and temp2 will have the result ready for read right after the assign, and the seed will have the value after a delta delay, assuming that you will not do the next iteration until next cycle.

如果常量是这样声明的，它将在代码中阐明意图:

It will clarify the intention in the code if constants are declared as such, doing:

constant MULTIPLY : std_logic_vector(31 downto 0) := x"41C64E6D";
constant ADD      : std_logic_vector(31 downto 0) := x"00003039";

对您的计算发表评论，然后VHDL设计将相乘的结果截断，从而执行以下操作:

A comment on you calculation, then the VHDL design truncates the result of the multiplication, thus doing:

种子=(种子* 1103515245)mod(2 ** 32)+ 12345

seed = (seed*1103515245) mod (2**32) + 12345

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