处理器是否使用Intel QuickPath Interconnect(QPI)来访问内存? [英] Is Intel QuickPath Interconnect (QPI) used by processors to access memory?

问题描述

我已阅读解决方案

是的，QPI用于访问多路系统上的所有远程内存，其设计和性能旨在以合理的方式支持此类访问(即延迟和带宽不会比本地访问差很多).

基本上，大多数x86多插槽系统都是 lighting ¹ NUMA:每个DRAM bank都连接到特定插槽的内存控制器:然后，该内存该插槽的本地内存，而其余的内存(附加到其他插槽)是远程内存.对远程内存的所有访问都通过QPI链接进行，在许多系统上， ² 完全是所有内存访问的一半，甚至更多.

因此，QPI被设计为低延迟和高带宽，以使此类访问仍能很好地执行.此外，除了纯内存 access 外，QPI是链接，套接字之间通过该链接发生缓存一致性，例如，通知其他套接字无效，已转换为共享状态的行等. >

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¹ 也就是说，NUMA因子非常低，通常在延迟和带宽方面小于2.

² 例如，在启用NUMA交错模式和4个套接字的情况下，您的访问权限中有75％是远程的.

I have read An Introduction to the Intel® QuickPath Interconnect. The document does not mention that QPI is used by processors to access memory. So I think that processors don't access memory through QPI.

Is my understanding correct?

解决方案

Yes, QPI is used to access all remote memory on multi-socket systems, and much of its design and performance is intended to support such access in a reasonable fashion (i.e., with latency and bandwidth not too much worse than local access).

Basically, most x86 multi-socket systems are lightly¹ NUMA: every DRAM bank is attached to a the memory controller of a particular socket: this memory is then local memory for that socket, while the remaining memory (attached to some other socket) is remote memory. All access to remote memory goes over the QPI links, and on many systems² that is fully half of all memory access and more.

So QPI is designed to be low latency and high bandwidth to make such access still perform well. Furthermore, aside from pure memory access, QPI is the link through which the cache coherence between sockets occurs, e.g., notifying the other socket of invalidations, lines which have transitioned into the shared state, etc.

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¹ That is, the NUMA factor is fairly low, typically less than 2 for latency and bandwidth.

² E.g., with NUMA interleave mode on, and 4 sockets, 75% of your access is remote.

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