即使RAM较慢，一个周期的指令也要占用一个周期吗? [英] Does a one cycle instruction take one cycle, even if RAM is slow?

问题描述

我正在使用嵌入式RISC处理器.我有一个基本的问题要解决.

I am using an embedded RISC processor. There is one basic thing I have a problem figuring out.

CPU手册明确指出，指令ld r1, [p1](在C中:r1 = * p1)需要一个周期.寄存器r1的大小为32位.但是，内存总线只有16位宽.那么如何在一个周期内获取所有数据?

The CPU manual clearly states that the instruction ld r1, [p1] (in C: r1 = *p1) takes one cycle. Size of register r1 is 32 bits. However, the memory bus is only 16 bits wide. So how can it fetch all data in one cycle?

推荐答案

时钟时间假定为全宽零等待状态内存.内核执行该指令所花费的时间是一个时钟周期.

The clock times are assuming full width zero wait state memory. The time it takes for the core to execute that instruction is one clock cycle.

有时每条指令占用不同数量的时钟周期.然后内存也相对较快，通常为零等待状态.在流水线之前还有一段时间，您必须刻录时钟周期，然后进行时钟周期解码，然后执行时钟周期，加上用于可变长度指令的额外时钟周期，以及如果指令具有存储器操作的额外时钟周期.

There was a time when each instruction took a different number of clock cycles. Memory was relatively fast then too, usually zero wait state. There was a time before pipelines as well where you had to burn a clock cycle fetching, then a clock cycle decoding, then a clock cycle executing, plus extra clock cycles for variable length instructions and extra clock cycles if the instruction had a memory operation.

如今，时钟速度很高，芯片占用的空间相对便宜，因此流水线和缓存的标准是一个时钟周期的加法或乘法.处理器时钟速度不再是性能的决定因素.内存相对昂贵且缓慢.因此，缓存(配置，数量和大小)，总线大小，内存速度，外设速度决定了系统的整体性能.通常，提高处理器时钟速度而不提高内存或外围设备的性能(如果有提高的话)将显示为最小，在某些情况下会使其变慢.

Today clock speeds are high, chip real estate is relatively cheap so a one clock cycle add or multiply is the norm, as are pipelines and caches. Processor clock speed is no longer the determining factor for performance. Memory is relatively expensive and slow. So caches (configuration, number of and size), bus size, memory speed, peripheral speed determine the overall performance of a system. Normally increasing the processor clock speed but not the memory or peripherals will show minimal if any performance gain, in some occasions it can make it slower.

内存大小和等待状态不是参考手册中时钟执行规范的一部分，它们只是在讨论内核本身以每条指令的时钟为单位要花费多少.如果是哈佛架构，其中指令和数据总线是分开的，则在存储周期中可能只有一个时钟.指令的获取至少发生在先前的时钟周期之前(如果不是在此之前)，因此在时钟周期的开始，指令准备就绪，解码并执行(读存储周期)发生在时钟的末尾的一个时钟周期内.一个时钟周期，读取结果被锁存到寄存器中.如果指令和数据总线是共享的，那么您可能会争辩说它仍然在一个时钟周期内完成，但是您无法获取下一条指令，因此那里存在一些停顿，它们可能会作弊并调用那个时钟循环.

Memory size and wait states are not part of the clock execution spec in the reference manual, they are talking about only what the core itself costs you in units of clocks for each of the instructions. If it is a harvard architecture where the instruction and data bus are separate, then one clock is possible with the memory cycle. The fetch of the instruction happens at least the prior clock cycle if not before that, so at the beginning of the clock cycle the instruction is ready, decode, and execute (the read memory cycle) happen during the one clock at the end of the one clock cycle the result of the read is latched into the register. If the instruction and data bus are shared, then you could argue that it still finishes in one clock cycle, but you do not get to fetch the next instruction so there is a bit of a stall there, they might cheat and call that one clock cycle.

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