多核处理器的MESI协议的详细信息 [英] details of MESI protocol for multicore processors

问题描述

对我来说，多核处理器的MESI协议的细节对我来说确实很重要，但是我在任何地方都找不到它们.甚至 http://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf 不没有足够的细节.例如:假定一个私有L1和共享L2缓存.如果行的状态在L1中是独占的，那么它在L2中是否也是独占的(或无效的，因为只有在一个高速缓存中才可能是行的独占状态)?显然，如果另一个内核写入了该行，则L1中以前排他的行的状态将变为无效，但是如何更改L2高速缓存行的状态呢?如果另一个内核读取了L1中的已修改行，是否将共享该行的新状态，并通过L2高速缓存写回主存储器，还是在L2中保持修改状态?等

The details of the MESI protocol for multicore processors would be really important for me, but I can't find them anywhere. Even http://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf doesn't contain enough detail. For instance: assume a private L1 and shared L2 cache. If the state of a line is exclusive in L1, then is it exclusive in L2 too (or invalid, because only in one cache could be the state of a line exclusive)? And clearly, if another core writes this line, the state of the previously exclusive line in L1 becomes invalid, but how is changing the state of the L2 cache line? If a modified line in L1 is read by another core, will be the new state of that line shared and is it written back to the main memory through the L2 cache, or stay modified in L2 too? etc.

推荐答案

找不到这些答案的原因是，由于传统协议未为分层缓存体系结构定义，因此MESI协议本身并未定义将要定义的内容.当您具有L1和L2缓存时，会发生这种情况.这取决于其他三个系统属性.

The reason you are having trouble finding these answers is because the traditional protocols were not defined for hierarchical cache architectures so the MESI protocol by itself doesn't define what will happen when you have an L1 and an L2 cache. It depends on three other system attributes.

如果将L2设计为不包含L1(即，保证L2和L1永远不会有公共高速缓存行)，则L1中的任何行在L2中将处于无效状态(基本上不存在) .

If the L2 is designed to be exclusive of the L1 (i.e., it is guaranteed that L2 and L1 can never have common cache lines), then any line in the L1 will be invalid state (basically not present) in the L2.

如果L2包含L1，即L1中的每一行也必须在L2中具有一个条目，则L2中的条目将包含一个描述符，该描述符说明哪个L1高速缓存中的行处于E状态.

If the L2 is inclusive of the L1, i.e., every line in the L1 must have an entry in the L2 as well, the entry in the L2 will contain a descriptor stating which L1 cache has the line in E state.

在从E或W阶段读取时，是否将该值写到L2或内存中取决于您的系统是否支持高速缓存到高速缓存的传输.在过去，当每个芯片是一个单核，而核到核的通信与读/写到存储器一样昂贵时，系统会将数据写到存储器中，并让另一个处理器读取它(这使得它们不支持缓存到缓存的传输).在多核中，通过内存进行通讯与在片上与其他内核进行通讯相比非常昂贵，因此当今几乎所有多核芯片都支持高速缓存到高速缓存的传输.因此，从E或W阶段进行的读取不通过写入存储器来提供服务.

Whether or not the value is written out to L2 or memory on a read from E or W stage depends on whether your system supports cache-to-cache transfers or not. In old day, when each chip was a single core, and core-to-core communication was as expensive as read/write to memory, systems would write the data to memory and make the other processor read it (this allowed them to not support cache-to-cache transfers). In multi-core, talking via memory is insanely expensive compared to talking to other cores on-chip, so almost all multi-core chips today support cache-to-cache transfer. Thus, a read from E or W stage is not serviced by writing to memory.

我希望这会有所帮助.

I hope this helps.

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