什么是“互锁管线"?像MIPS的首字母缩写词一样? [英] What is an "interlocked pipeline" as in the MIPS acronym?

问题描述

我正在研究MIPS处理器体系结构.

I am going through a MIPS procesor architecture.

按照本教程的说明:没有互锁管线阶段的微处理器 http://en.wikipedia.org/wiki/MIPS_architecture

As per this tutorial it states : Microprocessor without Interlocked Pipeline Stages http://en.wikipedia.org/wiki/MIPS_architecture

流水线的主要障碍是某些指令(例如除法)需要较长的时间才能完成，并且CPU 因此必须等待下一条指令传递到管道中.
解决此问题的一种方法是 使用一系列互锁，使各阶段指示它们很忙，从而暂停上游的其他阶段.
Hennessy的团队将这些联锁视为主要的性能障碍，因为它们必须与所有 CPU中的模块占用时间，并且似乎限制了时钟速度.
MIPS设计的主要方面 将所有指令的每个子阶段(包括缓存访问)都放入一个周期，从而删除了任何 需要互锁，并允许单周期吞吐量.

One major barrier to pipelining was that some instructions, like division, take longer to complete and the CPU therefore has to wait before passing the next instruction into the pipeline.
One solution to this problem is to use a series of interlocks that allows stages to indicate that they are busy, pausing the other stages upstream.
Hennessy's team viewed these interlocks as a major performance barrier since they had to communicate to all the modules in the CPU which takes time, and appeared to limit the clock speed.
A major aspect of the MIPS design was to fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.

此链接说:- https://www.cs.tcd.ie/Jeremy.Jones /vivio/dlx/dlxtutorial.htm

issue a "stall" instruction instead of a nop instruction upon a stall

互锁管道的缺点到底是什么?
为什么路由器习惯使用具有MIPS架构的处理器?

What exactly is Interlock Pipeline disadvantage ?
Why routers use to prefer Processors with MIPS Architecture ?

推荐答案

MIPS设计的一个主要方面是将所有指令的每个子阶段(包括缓存访问)都放入一个周期，从而消除了对互锁的任何需求，并允许单个周期的吞吐量.

A major aspect of the MIPS design was to fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.

但是在MIPS的更高版本中， http://cs.nyu.edu/幻灯片9，课程/spring02/V22.0480-002/vliw.pdf 重新引入了互锁:

But in later version of MIPS, http://cs.nyu.edu/courses/spring02/V22.0480-002/vliw.pdf slide 9, interlocking was reintroduced into architecure:

• 毕竟MIPS最初代表着类似 不带流水线级联锁的微处理器
• 因为新的实现(具有不同的内存延迟)将需要多个插槽，并且我们不希望代码的正确性取决于实现的版本.
• 因为其他说明仍然需要互锁(例如浮点数)
• 因为互锁不是那么痛苦

• After all MIPS originally stood for something like Microprocessor without interlocking pipeline stages
• Because new implementations (with different memory latencies) would have required more than one slot and we don’t like correctness of code being dependent on the version of the implementation.
• Because other instructions required interlocking anyway (e.g. floating-point)
• Because it is not that painful to do interlocking

因此，请考虑您的问题:

So, considering your questions:

互锁管道的缺点到底是什么?

What exactly is Interlock Pipeline disadvantage ?

联锁需要更复杂的硬件(CPU的控制单元)，在手绘晶体管和数十万个晶体管的CPU时代，设计和测试起来并不容易.他们选择了不互锁的CPU内核设计目标，但失败了.没有互锁，他们将无法生产兼容系列的商用芯片.

Interlocking needs more complex hardware (control unit of CPU), which was not so easy to design and test in the era of hand-drawn transistors and CPUs of 100s thousands of transistors. They selected the goal of designing CPU core without Interlocking, but they failed. They were unable to produce compatible series of commercial chips without Interlocking.

为什么路由器习惯使用具有MIPS架构的处理器?

Why routers use to prefer Processors with MIPS Architecture ?

从历史上看，它们可能是由于惯性和对基于MIPS的设备的投资(来自网络设备制造商和MIPS芯片制造商)而在第一个网络设备中流行，并在以后的设备中使用.

Historically they were popular in first network devices and were used in next devices possibly due to inertia and investments in MIPS-based devices (both from the network device makers and from MIPS chip makers).

检查本书"See MIPS Run"，作者Dominic Sweetman，第15、16、22页 http://books.google.com/books?id=kk8G2gK4Tw8C&pg=PR15

Check this book "See MIPS Run" By Dominic Sweetman, pages 15,16,22 http://books.google.com/books?id=kk8G2gK4Tw8C&pg=PR15

在1990年代中期，有几种易于使用的MIPS芯片:R4600，RM5200和RM7000.思科从1993年开始使用R4600，其下一型号具有64位总线和大型片上二级缓存.他们有足够的性能来驱动当时的路由器.

There were several easy accessible MIPS chips in the middle of 1990s, R4600, RM5200 and RM7000. The R4600 from 1993 was used by Cisco, next models had 64-bit bus and large on-chip L2 cache. They had enough performance to drive routers of the time.

在2010年代，我认为ARM上有路由器(有很多 2011年为78％) ;第二种架构是具有10％的ARC(请在PC或笔记本电脑上查看Intel vPro贴纸-如果有贴纸，则说明芯片组中具有ARC内核；它们还用于许多SSD控制器中). MIPS在该评级中仅排名第三，在100亿个内核总数中只有6％.

In 2010s, I think, there are routers on ARM (there is a lot of SoCs with network and ARM now). This is because ARM is most widely licensed architecture (in terms of licensed core count, 78% in 2011); second architecture is ARC with 10% (check the Intel vPro sticker on your PC or laptop - if you has sticker, you has ARC core in your chipset; they are also used in many SSD controllers). MIPS is only third in this rating with only 6% of 10 billion cores total in market.

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