相同类型的两个对象的未定义关系运算符-VHDL [英] Undefined relational operator for two objects of the same type - VHDL

问题描述

我目前在VHDL中有一个项目可以制造一个简单的自动售货机.我有一个std_logic信号来确定现金是否大于或等于商品的价格.成本是一个无符号常量，现金是一个无符号信号，但是尽管它们都是位长相等的无符号数字，但它告诉我>=运算符是不确定的.我查看了多个参考指南，发现所有两个参数必须具有相同的类型(它们是...)，所以我不确定为什么会引发此错误

I currently have a project in VHDL to make a simple vending machine. I have a std_logic signal to determine if the cash in is greater than or equal to the price of the item. The cost is an unsigned constant and the cash is an unsigned signal, but despite them both being unsigned numbers of equal bit length, it tells me the >= operator is undefined. I've looked in multiple reference guides, and all I can find is that the two arguments must be the same type (which they are...) so I'm not sure why it's throwing this error

我已经包含了正确的numeric_std库.

I have included the proper numeric_std library.

type STATE_TYPE is (RDY, CLCT, VND);
signal state : STATE_TYPE;
signal next_state : STATE_TYPE;

signal cash : unsigned (7 downto 0);
signal cashnew : unsigned (7 downto 0);

signal candy : std_logic;
signal candy_vend : std_logic;
constant cost_candy : unsigned := to_unsigned(60, 8);

signal chips : std_logic;
signal chips_vend : std_logic;
constant cost_chips : unsigned := to_unsigned(50, 8);

begin

candy <= candy1 or candy2 or candy3;
chips <= chip1 or chip2;

candy_vend <= candy and (cash >= cost_candy);
chips_vend <= chips and (cash >= cost_chips);

推荐答案

与其他语言一样，VHDL具有boolean类型.它是整数类型，并在软件包std.standard中提供.因此，此类型始终可见，因为默认情况下会引用此程序包.

As in other languages, VHDL has a boolean type. It is a integral type and provided in package std.standard. Thus this type is always visible, because this package is referenced by default.

与其他语言一样， relational 运算符也会产生布尔值.整数类型bit或数字逻辑类型std_logic都不是布尔值.布尔值具有true和false，其中，位具有0和1. std_logic类型支持9个值(9个值的逻辑，包括例如错误值).

Also like in other languages, a relational operator results in a boolean value. Neither the integral type bit nor the digital logic type std_logic is a boolean. Boolean has values true and false, where as bit has 0 and 1. The std_logic type supports 9 values (9-valued logic, including e.g. error values).

大多数运算符被定义为接受相同类型的左右操作数，同时再次返回该类型.

Most operators are defined to accept the right and left operands of the same type, while returning that type again.

因此您需要在某个时候将表达式转换回std_logic，因为candy_vend需要该类型.

So you need to convert your expression at some point back to std_logic, because candy_vend is expecting that type.

解决方案1:

candy_vend <= candy and ('1' when (cash >= cost_candy) else '0');

解决方案2:

candy_vend <= '1' when ((candy = '1') and (cash >= cost_candy)) else '0';

解决方案3:

function to_sl(value : boolean) return std_logic is
begin
  if value then
    return '1';
  else
    return '0';
  end if;
 end function;

用法:

 candy_vend <= candy and to_sl(cash >= cost_candy);
 candy_vend <= to_sl((candy = '1') and (cash >= cost_candy));

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