VHDL可以在同一文件中声明包和实体吗? [英] VHDL Can you declare a package and an entity in the same file?

问题描述

我试图将包和实体放置在同一个文件中，但是没有编译，这给了我一个错误:未知标识符std_logic，

I tried to place the package and the entity in the same file but it did not compile it gave me an error saying: unknown identifier std_logic,

我应该做些什么来将它们放入同一文件中?

is there something i should do to put them in the same file?

推荐答案

您在文件顶部提供的库声明适用于下一个设计单元(可能是您的程序包).

The library declarations that you provided at the top of the file apply to the next design unit (which is probably your package).

启动实体时，它是一个新的设计单元，并以一个空的库空间开头，因此您必须再次放入库声明.如果在一个给定的文件中放置多个实体，也会发生同样的情况-您必须为每个实体放置库子句.

When you start your entity, it is a new design unit and starts with an empty library space, so you have to put the library declarations in again. The same will happen if you put more than one entity in a given file - you have to put the library clauses in for each entity.

VHDL编译器完全不关心文件中的内容，它仅对其中的单元进行操作.因此，您可以在一个文件中包含一个entity，其中包含一些library声明，而在另一个文件中包含architecture.然后， not 库不需要在体系结构文件中重做，它们随实体一起提供.如果您仅 需要该体系结构的库，则可以将它们包含在体系结构语句之前(无论您是在一个文件中还是在两个文件中):

The VHDL compiler does not care at all what file anything is in, it only operates on the units within them. So you could have an entity in one file with some library declarations, and the architecture in another. The libraries do not then need to be redone in the architecture file, and they come in with the entity. If there are libraries that you only need for the architecture, they can be included just before the architecture statement (whether you are doing it in one file or two):

library ieee; 
use ieee.std_logic_1164.all;
entity foo
port ( 
   bar: std_logic; 
   etc...);
end entity;

-- could start a new file here, or not.
use ieee.numeric_std.all; -- not needed for the entity as it doesn't use unsigned types
architecture a of foo is
    signal counter : unsigned (10 downto 0);
begin
...
end architecture;

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