连续作业验证 [英] Continuous assignment verilog

问题描述

-此代码是使用Modelsim 10.2d在verilog中编写的。以下错误表明{cout，l3}分配存在一些问题。

-This code is written in verilog using Modelsim 10.2d.The errors below indicate there is some problem with {cout,l3} assignment.

module alu(a,b,bin,cin,op,cout,res);
input [31:0] a,b;
input [1:0] op;
input bin,cin;
reg [31:0] l1,l2,l3;
output cout;
output [31:0] res;

assign l1 = a & b;
assign l2 = a | b;

initial
if(bin == 1'b0)
  assign {cout,l3} = a + b + cin;
else
  assign {cout,l3} = a - b + cin;

mux4to1(l1,l2,l3,op,res);
endmodule

Error-
v(14): LHS in procedural continuous assignment may not be a net: cout.
v(16): LHS in procedural continuous assignment may not be a net: cout.

推荐答案

电线不能在 initial 或 always 块内分配。您应该将类​​型更改为 reg 。

wire can not be assigned inside an initial or always block. You should change the type to reg.

初始块仅在模拟开始时运行一次，而不是不断进行评估，因此应改为使用始终。

The initial block will only be run once at the start of the simulation, not continually evaluated, therefore you should use always instead.

//...
output reg cout;
//...

always @* begin
  if(bin == 1'b0) begin
    {cout,l3} = a + b + cin;
  end
  else begin
    {cout,l3} = a - b + cin;
  end
end

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