为什么没有为二进制减法设置溢出标志？ [英] why is there no overflow flag set for binary subtraction?

问题描述

我有基本的二进制数学问题。例如；

I have basic binary math question. For example;

reg [31:0] a = 32'hFFFF_FFFF; 
reg [31:0] b = 32'hFFFF_FFFF; 
reg [31:0] c = 0;

我知道c = a-b将导致为零，并且不会设置溢出标志。

I know c = a - b will result in zero and overflow flag will not be set.

我的理解是ALU使用2的subtrahend补码（运算符的右侧）并将其添加到被减数（运算符的左侧）。

My understanding is that ALU uses 2's complement of subtrahend (right side of operator) and adds it to minuend (left side of operator).

因此，规则b中存储的值的2s补码为32’h1。现在，如果将其添加到reg a，我将得到32个零和一个1，这是溢出的。那为什么不设置溢出标志呢？

So 2s complement for value stored in reg b is 32'h1. Now, if I add this to reg a, I will get 32 zeros and a 1, which is overflow. Then why is not overflow flag set?

即使我将reg c的宽度更改为33，c [32]也不设置为1。我知道当减去两个相等的数字时，不会溢出但是当我进行2s补数运算时，我会溢出。

Even if I change width of reg c to 33, c[32] is not set to 1. I understand that when two equal numbers are subtracted, there is no overflow but I get an overflow when I do 2s complement math.

让我们清除一下我头脑中的困惑。
谢谢您的时间。

Let help me clear this confusion in my head. Thank you for your time.

推荐答案

您必须查看两个补码是什么。因此，在您的示例中， a 和 b 是32位向量，所有位都设置为 1：

you have to look at what two's complement is. So, in your example a and b are 32-bit vectors with all bits set to '1':

 a[31:0] = 32'hFFFF_FFFF;

两个的补码是32’h0000_0001;因此，将其添加到 b 会将所有设置为 0 并溢出位 33 由于操作的宽度为32位而被截断。

two's complement of this is 32'h0000_0001; so, adding it to b will cause all set to 0 and overflow bit 33 truncated because the width of the operation is 32 bits.

现在，假设您有一个33位向量

Now, supposedly you have a 33 bit vector

a[32:0] = 33'hFFFF_FFFF;

两者的补码将为 33'h1_OOOO_OOO1 。因此，如果将其添加到33位向量 33’hFFFF_FFFF 中，则所有33位仍将等于 0。如果将更多位添加到 a ，则将更多 1 添加到msb侧： 34 'h3_0000_0001 ，...

the two's complement will be 33'h1_OOOO_OOO1. So, if you add it to a 33-bit vector 33'hFFFF_FFFF, you will still have all 33 bits equal to '0'. If you add more bits to a, more 1 be added to the msb side: 34'h3_0000_0001, ...

并且，如果 c 大于操作上下文，对于无符号变量，它将始终为0扩展，否则为符号扩展。

And, if c is wider than operation context, it will always be 0-extended, for unsigned vars, otherwise sign-extended.

因此，您总是会遇到溢出位为在操作宽度之外，并被截断。这是通过操作宽度的LRM要求来保证的。

As a result, you will always end up in the situation when the overflow bit is outside of the operation width, and is truncated. This is guaranteed by LRM requirement of the operation width.

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