Spartan-3E上的随机数生成 [英] Random number generation on Spartan-3E

问题描述

我需要在Spartan-3E FPGA上为我的遗传算法生成伪随机数，我想在Verilog中实现它:您能对此提供任何指导吗?

I need to generate pseudo-random numbers for my genetic algorithm on a Spartan-3E FPGA and i want to implement it in verilog: could you give me any pointers on this?

推荐答案

通常，您将使用 IEEE.math_real 统一函数

Typically you'd use the IEEE.math_real uniform function

use IEEE.math_real.all;
procedure UNIFORM (variable Seed1,Seed2:inout integer; variable X:out real);

但是对伪随机数生成器(PRNG)进行一点研究，您会发现许多简单的变体

But do a tiny bit a research on pseudo random number generators (PRNGs) and you'll find many variants that are simple LFSR's - which look remarkably similar to CRC generators.

如果您要从现有的有效PRNG开始滚动自己的资源，则有以下几种资源:

Here are several resources if you want to roll your own starting from existing, working PRNGs:

http://www.opencores.org/?do=project&who = systemc_rng

http://verificationguild.com/modules.php ?name = Downloads& d_op = viewdownload& cid = 3

这是CRC VHDL代码生成器:

Here's a CRC VHDL code generator:

http://www.easics.be/webtools/crctool

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