不同cpu AMD/Intel上的物理核心和逻辑核心 [英] Physical core and Logical cores on different cpu AMD/Intel

问题描述

任何人都可以确认例如Intel i3 CPU具有2个物理核心和4个逻辑核心，因此如果我将进程亲和力设置为Core#0，则意味着我在第一个物理核心上设置了1个逻辑核心，但是如果我在Core上进行了设置#1，这意味着我在第一个物理核心1 HyperThreading核心上进行了设置，

但是，由于AMD CPU具有某种类型的模块"，因此如何处理?至少我在互联网上读到的东西

如何使用AMD CPU?

Intel是否始终具有相同的物理内核，其中包含1个逻辑内核和1个HT内核?

AMD物理核心组合怎么样?

解决方案

某些Intel CPU已禁用超线程，例如四核i5 CPU通常禁用HT.例如 Skylake台式机芯片上装有4c8t(4核/8线程) i7型号，i5芯片上的4c4t(不带HT的四核)和i3芯片上的2c4t(带HT的双核).

超线程仅使用多核/多路SMP系统引导和发现CPU的现有方式.支持HT的OS必须检查每个CPU的物理ID，以查明它们中的哪个与另一个逻辑CPU共享一个物理核心.

如果在BIOS中禁用了HT，则系统仅表示每个物理内核具有一个CPU，而不是2(在Xeon Phi中为4).

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从逻辑核心到物理核心的映射未标准化.

在我的SKL台式机上(华硕Z170 Pro Gaming主板中的i7-6700k)，Linux将我的内核检测为:

log   phys
 0     0
 1     1
 2     2
 3     3
 4     0
 5     1
 6     2
 7     3

但是在Haswell笔记本电脑上，是

log   phys
 0     0
 1     0
 2     1
 3     1

IDK(如果有系统具有怪异的逻辑->物理映射)；我认为要么包装

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但是AMD CPU怎么样呢，因为它们至少有一些我在互联网上阅读的模块"

推土机家族使用成对的弱整数内核共享SIMD/FPU单元和某些缓存，并将其称为集群".这对单线程工作负载不是很好(因为两个整数内核之一处于空闲状态)，但是当有足够多的线程来使所有内核保持繁忙时，影响比英特尔的HT好.

Ryzen是一种细粒度的 SMT(同步多线程)架构(通用CPU- HT的架构术语)与英特尔非常相似，但是拥有更广泛的渠道.

Ryzen将其核心组织为4个集群，这些集群共享一个L3缓存( https://www.reddit.com/r/hardware/comments/6s1m80/why_did_amd_design_ryzen_as_2_quadcore_ccxs/).两个或多个CCX内核集群之间存在互连. 这与SMT无关.

Can anyone confirm that for example Intel i3 CPU has 2 physical cores and 4 logical cores, so if I set Process affinity to Core #0 so that means I set on first physical cores 1 logical core, but if I set on Core #1 so it means I set on first physical core 1 HyperThreading core,

But how about AMD CPU, since they have some kind of "modules" at least what I read on internet,

How to work with AMD CPUs?

And does Intel ALWAYS have this same physical core contains 1 logical and 1 HT core?

How about AMD physical core combo?

解决方案

Some Intel CPUs have hyperthreading disabled, e.g. quad core i5 CPUs usually have HT disabled. e.g. Skylake desktop chips have 4c8t (4 cores / 8 threads) on the i7 models, 4c4t on the i5 chips (quad core without HT), and 2c4t on the i3 chips (dual core with HT).

Hyperthreading just uses the already-existing way that multi-core / multi-socket SMP systems boot and discover CPUs. An HT-aware OS has to check the physical ID of each CPU to find out which if any of them share a physical core with which other logical CPU.

If you disable HT in the BIOS, the system only presents itself as having one CPU per physical core, instead of 2. (Or 4 in Xeon Phi).

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The mapping from logical core to physical core isn't standardized.

On my SKL desktop (i7-6700k in an Asus Z170 Pro Gaming mobo), Linux detects my cores as:

log   phys
 0     0
 1     1
 2     2
 3     3
 4     0
 5     1
 6     2
 7     3

But on a Haswell laptop, it was

log   phys
 0     0
 1     0
 2     1
 3     1

IDK if any system have weirder logical->physical mappings; I think either wrapping

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but how about AMD CPU since they got somekind of "modules" atleast what I read on internet

Bulldozer-family uses pairs of weak integer cores sharing a SIMD / FPU unit and some cache, and calls that a "cluster". It's not good for single-threaded workloads (because one of the two integer cores sits idle), but more effecting than Intel's HT when there are enough threads to keep all the cores busy.

Ryzen is a fine-grained SMT (Simultaneous Multithreading) architecture (the generic CPU-architecture term for what HT is) that's very much like Intel's, but with an even wider pipeline.

Ryzen organizes its cores into clusters of 4 which share an L3 cache (https://www.reddit.com/r/hardware/comments/6s1m80/why_did_amd_design_ryzen_as_2_quadcore_ccxs/). There's an interconnect between two or more CCX clusters of cores. This is unrelated to SMT.

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