如何在合成Verilog中包括时间延迟? [英] How to include time delay in synthesized verilog?

问题描述

我正在尝试用verilog编写可综合代码，其中要求包括几秒钟的时间延迟.我已经使用#delay进行了仿真，但是合成器不接受.

I am trying to write a synthesizable code in verilog, in which I require to include a time delay of few seconds. I have done the simulation using #delay, but this is not acceptable by synthesizer.

在合成FSM的过程中，FSM的状态不是基于某种条件而改变，而是经过几秒钟的时间延迟后，我想要上面的时间延迟方法. FSM必须在4秒后将状态从state_1切换到state_2，然后在2秒后将state_2切换到state_3，依此类推.

In the process of synthesizing a FSM, which change its states not based on some condition but after few seconds of time delay, I want the above time delay method. FSM has to switch states say from state_1 to state_2 after 4 seconds and state_2 to state_3 after 2 seconds and so on.

推荐答案

在延时后切换状态，希望这段代码对您有所帮助.

For switching the states after a time delay,I hope this code helps.

current_state=state_1;
for(i=0;i<=timedelay*freq;i=i+1)
@posedge;
current_state=state_2;

current_state=state_1;
for(i=0;i<=timedelay*freq;i=i+1)
@posedge;
current_state=state_2;

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