为什么我不能将值输入到inout类型? [英] Why I can not input value to inout type?

问题描述

• 我是根据此此处的图片
创建的代码
• 这是错误图片此处的图片
• 该课程为具有三态输出的四路总线收发器

• I create this code from this curcuit Image Here
• And this is Error image Image Here
• This curcuit is Quadruple Bus Transcievers with 3-state outputs

病毒码

module Q52QuadrupleBus3Stlate(GAB,GBA,A,B);
    inout [3:0] A,B;
    input GAB,GBA;
    reg winA,winB;
    assign  B = (GAB==1&&GBA==0) ? winA : 4'hz;
    assign  A = (GAB==0&&GBA==1) ? winB : 4'hz;
    always @ (GAB or GBA)
    begin
        winA <= A;
        winB <= B;
    end
endmodule

测试平台

`timescale 1ps / 1ps
module Q52TestBench;
    reg GAB;
    reg GBA;
    // Bidirs
    wire [3:0] A;
    wire [3:0] B;
    parameter step = 10000;
    Q52QuadrupleBus3Stlate uut (GAB,GBA,A,B);
    initial begin
            GAB = 0;
            GBA = 0;
            A = 0; B = 0;
    #step GAB = 1;
    #step GBA = 0;
    #step GAB = 0;
    #step GBA = 1;
    #step GAB = 1;
    #step GBA = 0;
    #step GAB = 0;
    #step GBA = 1;
    #(step*10) $finish;
    end
endmodule

推荐答案

在Verilog中:

• a wire必须由实例化模块的output(或inout)或assign语句

• a wire must be driven by the output (or inout) of an instantiated module or an assign statement

a reg必须由always或initial块驱动.

a reg must be driven by an always or initial block.

决定信号是reg还是电线的决定主要是由哪种代码驱动信号来决定的.实例化模块(uut)的输出和initial块均驱动​​信号A和B.因此，您有一个难题.幸运的是，有一个简单的解决方案，通常在Verilog中使用.

The decision as to whether a signal is to be a reg or a wire is driven primarily by what kind of code is driving the signal. Your signals A and B are driven by both the output of an instantiated module (uut) and by an initial block. So, you have a dilemma. Fortunately, there is a simple solution to this, which is commonly used in Verilog.

要从initial或always块驱动inout，除了连接到模块inout端口(在您的情况下为A和B)的电线外，还需要一些额外的信号.您需要一个reg来与每个字母对应:

To drive an inout from an initial or always block, you need some extra signals in addition to the wires connected to your module inout ports (A and B in your case). You need a reg to correspond with each:

reg  [3:0] Ain;
reg  [3:0] Bin;

以及与每个信号对应的启用信号

and an enable signal to correspond with each:

reg        Aen;
reg        Ben;

然后，您需要使用assign语句实现一些三态驱动程序:

Then you need to implement some tri-state drivers using assign statements:

assign A = Aen ? Ain : 'bz;
assign B = Ben ? Bin : 'bz;

您需要从initial块驱动reg，而不是wire s:

You need to drive the regs from the initial block, not the wires:

        Ain = 0; Bin = 0;

最后，您还需要从同一initial块驱动使能信号:

and finally, you also need to drive the enable signals from the same initial block:

        Aen = 1; Ben = 1;

这是完整的代码:

`timescale 1ps / 1ps
module Q52TestBench;
    reg GAB;
    reg GBA;
    // Bidirs
    wire [3:0] A;
    wire [3:0] B;
    reg  [3:0] Ain;
    reg  [3:0] Bin;
    reg        Aen;
    reg        Ben;
    parameter step = 10000;
    Q52QuadrupleBus3Stlate uut (GAB,GBA,A,B);
    assign A = Aen ? Ain : 'bz;
    assign B = Ben ? Bin : 'bz;
    initial begin
            GAB = 0;
            GBA = 0;
            Ain = 0; Bin = 0;
            Aen = 1; Ben = 1;
    #step GAB = 1;
    #step GBA = 0;
    #step GAB = 0;
    #step GBA = 1;
    #step GAB = 1;
    #step GBA = 0;
    #step GAB = 0;
    #step GBA = 1;
    #(step*10) $finish;
    end
endmodule

https://www.edaplayground.com/x/5biz

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