PCIe总线上的写入是原子的吗? [英] Are writes on the PCIe bus atomic?

问题描述

我是PCIe的新手，所以这可能是一个愚蠢的问题.这似乎是询问PCIe接口的相当基本的信息，但是我很难找到答案，因此我猜测我缺少一些使答案显而易见的信息.

I am a newbie to PCIe, so this might be a dumb question. This seems like fairly basic information to ask about PCIe interfaces, but I am having trouble finding the answer so I am guessing that I am missing some information which makes the answer obvious.

我有一个系统，其中有一个ARM处理器(主机)通过PCIe(设备)与Xilinx SoC通信. SoC中的端点也是ARM处理器.

I have a system in which I have an ARM processor (host) communicating to a Xilinx SoC via PCIe (device). The endpoint within the SoC is an ARM processor as well.

外部ARM处理器(主机)将通过PCIe写入SoC的ARM处理器(设备)的寄存器空间.这将命令SoC做各种事情.相对于SoC(设备)，该寄存器空间将是只读的.外部ARM处理器(主机)将对此寄存器空间进行写操作，然后向中断发出信号，以向SoC指示已写入新参数，并应对其进行处理.

The external ARM processor (host) is going to be writing to the register space of the SoC's ARM processor (device) via PCIe. This will command the SoC to do various things. That register space will be read-only with respect to the SoC (device). The external ARM processor (host) will make a write to this register space, and then signal an interrupt to indicate to the SoC that new parameters have been written and it should process them.

我的问题是:相对于SoC(设备)的读取，是否保证由外部ARM(主机)进行的写入是原子的?在常规共享内存的情况下，对单个字节的写操作被保证是原子操作(即，您永远不能处于读取器已读取字节的前2位，但在读取后6位之前的情况).编写者将它们替换为新值，从而导致产生垃圾数据). PCIe也是如此吗?如果是的话，原子性的单位"是什么?单个事务中的所有字节是相对于整个事务而言是原子的，还是每个字节仅相对于自身而言是原子的?

My question is: are the writes made by the external ARM (host) guaranteed to be atomic with respect to the reads by the SoC (device)? In conventional shared memory situations, a write to a single byte is guaranteed to be an atomic operation (i.e. you can never be in a situation where the reader had read the first 2 bits of the byte, but before it reads the last 6 bits the writer replace them with a new value, leading to garbage data). Is this the case in PCIe as well? And if so, what is the "unit" of atomic-ness? Are all bytes in a single transaction atomic with respect to the entire transaction, or is each byte atomic only in relation to itself?

这个问题有意义吗?

我基本上想知道在我所处的情况下需要多大程度的内存保护.如果有可能，我希望避免在两个处理器都运行RTOS时锁定内存区域，并且避免内存锁定会使设计更简单.

Basically I want to know to what extent memory protection is necessary in my situation. If at all possible, I would like to avoid locking memory regions as both processors are running RTOSes and avoiding memory locks would make design simpler.

推荐答案

因此，在原子性问题上，多次提到了PCIe 3.0规范(我只有一个).

So on the question of atomicity the PCIe 3.0 specification (only one I have) is mentioned a few times.

首先，您有第6.5节锁定的交易，这可能不是您所需要的，但无论如何我都希望对其进行记录.基本上，这是您之前所描述的最坏的情况.

First you have SECTION 6.5 Locked Transactions this is likely not what you need but I want to document it anyway. Basically it's the worst case scenario of what you were describing earlier.

需要锁定交易支持才能防止使用旧版软件的系统出现死锁 导致对I/O设备的访问

Locked Transaction support is required to prevent deadlock in systems that use legacy software which causes the accesses to I/O devices

但是您仍然需要按照说明正确使用此功能.

But you need to properly check using this anyway as it notes.

如果与锁定序列相关的任何读取未成功完成，则请求者必须 假设不再确保锁的原子性，并且 请求者和完成者不再被锁定

If any read associated with a locked sequence is completed unsuccessfully, the Requester must assume that the atomicity of the lock is no longer assured, and that the path between the Requester and Completer is no longer locked

话虽如此，但第6.15节原子操作(AtomicOps)"更像您感兴趣的内容.您可以使用AtomicOps指令执行3种类型的操作.

With that said Section 6.15 Atomic Operations (AtomicOps) is much more like what you are interested in. There are 3 types of operations you can perform with the AtomicOps instruction.

FetchAdd(获取和添加):请求包含单个操作数，即"add"值

FetchAdd (Fetch and Add): Request contains a single operand, the "add" value

交换(无条件交换):请求包含单个操作数，即交换"值

Swap (Unconditional Swap): Request contains a single operand, the "swap" value

CAS(比较和交换):请求包含两个操作数，一个比较"值和一个交换"值

CAS (Compare and Swap): Request contains two operands, a "compare" value and a "swap" value

阅读第6.15.1节，我们注意到这些说明主要是针对单个总线上存在多个生产者/消费者的情况而实施的.

Reading Section 6.15.1 we see mention that these instructions are largely implemented for cases where multiple producers/consumers exist on a singular bus.

AtomicOps启用高级同步机制，当存在以下情况时特别有用 需要以非阻塞方式同步的多个生产者和/或多个消费者.例如，多个生产者可以安全地加入一个公共队列，而无需任何显式锁定.

AtomicOps enable advanced synchronization mechanisms that are particularly useful when there are multiple producers and/or multiple consumers that need to be synchronized in a non-blocking fashion. For example, multiple producers can safely enqueue to a common queue without any explicit locking.

在本规范的其余部分中搜索，除了与这些AtomicOps有关的部分之外，我几乎没有提及原子性.对我而言，这意味着该规范仅在使用这些操作时才确保此类行为，但是，围绕执行此操作的原因的上下文表明，它们仅在存在多生产者/消费者环境的情况下才期待此类问题，而您显然没有.

Searching the rest of the specification I find little mention of atomicity outside of the sections pertaining to these AtomicOps. That would imply to me that the spec only insures such behavior when these operations are used however the context around why this was implemented suggests that they only expect such questions when a multi producer/consumer environment exists which yours clearly does not.

我建议您回答问题的最后一个地方是第2.4节交易排序" .要注意的是，我很确定交易超越"其他交易的想法只有在中间进行切换才有意义交换机可以做出这样的决定，只要您将总线上的位放回原位，就不会再返回了.因此，这可能仅在您在其中放置开关的情况下适用.

The last place I would suggest looking to answer your question is Section 2.4 Transaction Ordering To note I am fairly sure the idea of transactions "passing" others only makes sense with switches in the middle as these switches can make such decisions, once your put bits on the bus in your case there is no going back. So this likely only applies if you place a switch in there.

您所关心的是写入是否可以绕过读取.写被发布，读不被发布.

Your concern is can a write bypass a read. Write being posted, read being non-posted.

A3, A4 A Posted Request must be able to pass Non-Posted Requests to avoid deadlocks.

因此，通常，允许写操作绕过读取操作以避免死锁.

So in general the write is allowed to bypass the read to avoid deadlocks.

由于这种担忧，我认为写操作不可能绕过系统上的读操作，因为总线上没有设备可以进行事务重新排序.由于您有RTOS，因此我非常怀疑它们会在发送前对PCIe事务进行排序并重新排序，尽管我个人没有对此进行调查.

With that concern raised I do not believe it is possible for the write to bypass the read on your system since there is no device on the bus to do this transaction reordering. Since you have RTOSes I highly doubt they are enquing the PCIe transactions and reordering them before sending although I have not looked into that personally.

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