字节序与堆栈增长方向之间的关系 [英] Relation between endianness and stack-growth direction
问题描述
处理器的字节序与堆栈增长的方向之间是否存在关系？
例如， x86体系结构是小尾数，堆栈向下增长（即，每次执行 push 操作时，堆栈都从最高地址开始向较低地址增长）。同样，在 big endian 的 SPARC体系结构中，堆栈从最低地址开始，然后向上扩展到更高的地址。
几乎在所有体系结构中都可以看到这种关系模式。 我相信这种未提及的约定一定有原因。可以从计算机体系结构或OS的角度来解释吗？这是对处理器内部微代码的某种优化吗？这在某种程度上对内核有帮助吗？还是其他原因？
提前感谢！
堆栈增长方向与整数字节顺序正交。
在较宽的整数（字）中字节顺序与是否是否为零之间存在零联系。堆栈推加或减堆栈指针。就推送而言，存储数据只是一个操作。
将寄存器宽度的整数映射到内存中的字节使用的是与堆栈指针inc不同的硬件/ dec逻辑；我认为正常的设计将使用非推送/流行存储/加载所经历的相同硬件，并且像对待 word的任何其他存储一样，从推送中对待存储。并不是一种奇怪的每次只能一个字节地递增堆栈指针的事情。
这种关系模式是
嗯，不是真的。许多现代的RISC ISA（例如MIPS，PowerPC，ARM）具有可选的字节序 1 ，并且不连接到堆栈增长方向。
>方向是什么显示在大多数主流系统上，堆栈增长的方向通常是按约定或按要求降低的，包括按大端顺序排列的系统。
根据该问答的答案，SPARC上的主流OS / ABI选择向下扩展堆栈。在SPARC上，可以选择向上，但是像其他系统一样，通常的选择是向下。
这可以从计算机体系结构或操作系统的角度来解释吗？
我们可以解释的是，向下是事实上的标准。 IDK为什么SPARC会费心选择向上。显然，没有分页/虚拟内存，在可用内存顶部的堆栈是自然的，而静态代码/数据在底部的固定地址。 https://softwareengineering.stackexchange.com/questions/137640/why-does-堆栈向下生长
这就是我们到达这里的方式。
在某些地方ISA，例如MIPS，堆栈增长方向完全由软件确定。硬件并没有隐式/异步地使用堆栈，也没有推/弹出指令使一种或另一种方式更有效。
但是通常，选择仍然是向下。
其他ISA类似于x86，其中异步中断将内容推入内核堆栈，强制一个方向。或者至少在一种方式上存在偏见，即为一个方向提供有效的推入/弹出操作（例如ARM Thumb和x86的 push / pop ）。更不用说x86的 call / ret 指令，这些指令推/弹出一个返回地址，而不仅仅是编写链接寄存器。 / p>
如果没有选择的方向，则大多数ISA中的一个固定方向是向下的，但是@chux表示PIC24的堆栈向上增长。
我很确定所有这些都有大端和小端的例子，或者至少可以配置成大端的双端系统
脚注1：一些特定的ARM或MIPS CPU的字节序为硬连线，无法在运行时选择，因为它基本上是一项无用的功能，并且浪费了嵌入式硅。不确定现代POWER硬件； Godbolt编译器浏览器（ https://godbolt.org/ ）同时具有PowerPC64和PowerPC64le编译器，但事实并非如此。告诉我们它们是否仍然相关。
Is there a relation between endianness of a processor and the direction of stack growth?
For example, x86 architecture is little endian and the stack grows downwards (i.e. it starts at highest address and grows towards lower address with each push operation). Similarly, in SPARC architecture, which is big endian, the stack starts at lowest address and grows upwards towards higher addresses.
This relationship pattern is seen in almost all architectures. I believe there must be a reason for this unsaid convention. Can this be explained from computer architecture or OS point of view? Is this for some optimization in the microcode inside the processor? Does this aid the kernel in some way? Or may be other reason?
Thanks in advance!
Stack grown direction is orthogonal to integer endianness.
There is zero connection between the order of bytes within a wider integer (word), and whether a stack push adds or subtracts from the stack pointer. As far as a push is concerned, storing the data is a single operation.
Mapping a register-width integer to bytes in memory uses different hardware from the stack-pointer inc/dec logic; I assume the normal design would be to use the same hardware that non-push/pop stores/loads go through, and just treat the store from a push like any other store of a "word". Not any kind of weird one-byte-at-a-time thing that increments the stack pointer one by one.
This relationship pattern is seen in almost all architectures.
Uhhhh, not really. Many modern RISC ISAs (e.g. MIPS, PowerPC, ARM) have selectable endianness1, and that's not connected to stack-growth direction.
What is the direction of stack growth in most modern systems? shows that on most mainstream systems, the stack growth direction is typically down either by convention or by requirement, including on big-endian systems.
According to the answer on that Q&A, mainstream OSes / ABIs on SPARC choose to grow the stack downward. Upward is an option on SPARC, but the normal choice is downward like other systems.
Can this be explained from computer architecture or OS point of view?
What we can explain is that downward is the de-facto standard. IDK why SPARC bothered to make upward an option. Stack at the top of available memory, with static code/data at fixed addresses at the bottom, is obviously natural without paging / virtual memory. https://softwareengineering.stackexchange.com/questions/137640/why-does-the-stack-grow-downward
So that's how we got here.
On some ISAs, e.g. MIPS, the stack-grown direction is purely determined by software. The hardware doesn't implicitly / asynchronously use the stack, and there aren't push/pop instructions that make it more efficient to go one way or the other.
But the normal choice is still downward.
Other ISAs are like x86 where async interrupts push stuff onto the kernel stack, forcing one direction. Or at least have a bias in one way, by providing efficient push/pop for one direction (like ARM Thumb, and like x86's push/pop). Not to mention x86's call/ret instructions that push/pop a return address instead of just writing a link register.
If there is no choice of direction, the one fixed direction is downward in most ISAs, but @chux comments that PIC24 has upward stack growth.
I'm pretty sure there are big and little-endian examples of all of these, or at least bi-endian systems that can be configured as big or little-endian.
Footnote 1: Some specific ARM or MIPS CPUs have their endianness hard-wired, not runtime selectable, because it's basically a useless feature and waste of silicon for embedded. Not sure about modern POWER hardware; the Godbolt compiler explorer (https://godbolt.org/) has both PowerPC64 and PowerPC64le compilers, but that doesn't tell us whether they're both still relevant.
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