VHDL：基于非常快的时钟创建非常慢的时钟脉冲 [英] VHDL: creating a very slow clock pulse based on a very fast clock

问题描述

（我将其发布到EE中，但似乎这里还有更多的VHDL问题...）

背景：我将Xilinx Spartan-6LX9 FPGA与Xilinx ISE 14.4（Webpack）一起使用。

Background: I'm using the Xilinx Spartan-6LX9 FPGA with the Xilinx ISE 14.4 (webpack).

我偶然发现了令人恐惧的 PhysDesignRules：372-今天发出门控时钟警告，我认为目前对此进行了大量讨论。共识似乎是使用FPGA上的DCM之一进行时钟划分，但是...我的DCM似乎无法从32 MHz升至4.096 KHz（根据向导，它的最低频率为5MHz，基于32MHz ...并且出于这种低频目的而尝试链接多个DCM似乎是荒唐的。）

I stumbled upon the dreaded "PhysDesignRules:372 - Gated clock" warning today, and I see there's a LOT of discussion out there concerning that in general. The consensus seems to be to use one of the DCMs on the FPGA to do clock division but... my DCM doesn't appear to be capable of going from 32 MHz to 4.096 KHz (per the wizard it bottoms out at 5MHz based on 32MHz... and it seems absurd to try to chain multiple DCMs for this low-frequency purpose).

我目前的设计使用clk_in来计算指定值（ 15265），将该值重置为零并切换clk_out位（因此，我的占空比为50％，FWIW）。它可以完成工作，并且我可以轻松地使用clk_out的上升沿驱动设计的下一个阶段。它似乎可以正常工作，但是... 门控时钟（即使它不在时钟偏斜的范围内，恕我直言也非常重要）。 （注意：所有时钟测试都是在对给定时钟敏感的进程中使用riseing_edge（）函数完成的。）

My current design uses clk_in to count up to a specified value (15265), resets that value to zero and toggles the clk_out bit (so I end up with a duty cycle of 50%, FWIW). It does the job, and I can easily use the rising edge of clk_out to drive the next stage of my design. It seems to work just fine, but... gated clock (even though it isn't in the range where clock skew would IMHO be very relevant). (Note: All clock tests are done using the rising_edge() function in processes sensitive to the given clock.)

所以，我的问题是：

• 如果我们要谈论的是从快得多的 clk_in导出相对慢的clk_out，那么门控是否仍被认为是不好的？ 或者这种计数到x并发送脉冲的事情对于FPGA来说是很典型的 ，以产生KHz范围内的时钟，而是可能触发其他一些不必要的副作用

• If we're talking about deriving a relatively slow clk_out from a much faster clk_in, is gating still considered bad? Or is this sort of "count to x and send a pulse" thing pretty typical for FPGAs to generate a "clock" in the KHz range and instead some other unnecessary side-effect may be triggering this warning instead?

是否有更好的方法可以从MHz范围的主时钟创建低KHz范围的时钟，请记住在这里使用多个DCM似乎是过大的（如果在非常低的输出频率下完全有可能）？我意识到50％的占空比可能是多余的，但假设有一个时钟输入，而使用板载DCM却没有 ，那么用FPGA还会执行主要的时钟分频吗？

Is there a better way to create a low KHz-range clock from a MHz-range master clock, keeping in mind that using multiple DCMs appears to be overkill here (if it's possible at all given the very low output frequency)? I realize the 50% duty cycle may be superfluous but assuming one clock in and not using the on-board DCMs how else would one perform major clock division with an FPGA?

编辑：给定以下内容（其中CLK_MASTER是32 MHz输入时钟，而CLK_SLOW是所需的慢速时钟，而LOCAL_CLK_SLOW是一种存储方式整个占空比周期的时钟状态），我了解到此配置会引发警告：

Given the following (where CLK_MASTER is the 32 MHz input clock and CLK_SLOW is the desired slow-rate clock, and LOCAL_CLK_SLOW was a way to store the state of the clock for the whole duty-cycle thing), I learned that this configuration causes the warning:

architecture arch of clock is
    constant CLK_MASTER_FREQ: natural := 32000000; -- time := 31.25 ns
    constant CLK_SLOW_FREQ: natural := 2048;
    constant MAX_COUNT: natural := CLK_MASTER_FREQ/CLK_SLOW_FREQ;
    shared variable counter: natural := 0;
    signal LOCAL_CLK_SLOW: STD_LOGIC := '0';
begin
    clock_proc: process(CLK_MASTER)
    begin
        if rising_edge(CLK_MASTER) then
            counter := counter + 1;
            if (counter >= MAX_COUNT) then
                counter := 0;
                LOCAL_CLK_SLOW <= not LOCAL_CLK_SLOW;
                CLK_SLOW <= LOCAL_CLK_SLOW;
            end if;
        end if;
    end process;
end arch;

而此配置不会引起警告：

Whereas this configuration does NOT cause the warning:

architecture arch of clock is
    constant CLK_MASTER_FREQ: natural := 32000000; -- time := 31.25 ns
    constant CLK_SLOW_FREQ: natural := 2048;
    constant MAX_COUNT: natural := CLK_MASTER_FREQ/CLK_SLOW_FREQ;
    shared variable counter: natural := 0;
begin
    clock_proc: process(CLK_MASTER)
    begin
        if rising_edge(CLK_MASTER) then
            counter := counter + 1;
            if (counter >= MAX_COUNT) then
                counter := 0;
                CLK_SLOW <= '1';
            else
                CLK_SLOW <= '0';
            end if;
        end if;
    end process;
end arch;

因此，在这种情况下，都是因为缺少其他内容（就像我说的那样，占空比本来是有趣的，但最后并不是必需的，并且当时本地时钟位的切换似乎很聪明……）我基本上是在正确的轨道上。

So, in this case it was all for lack of an else (like I said, the 50% duty cycle was originally interesting but wasn't a requirement in the end, and the toggle of the "local" clock bit seemed quite clever at the time...) I was mostly on the right track it appears.

目前我还不清楚的是为什么使用计数器（存储很多位）不会引起警告，而是存储和切换输出位是引起警告。有想法吗？

What's not clear to me at this point is why using a counter (which stores lots of bits) isn't causing warnings, but a stored-and-toggled output bit does cause warnings. Thoughts?

推荐答案

如果您只需要时钟来驱动另一部分对于FPGA中的逻辑，简单的答案是使用时钟使能。

If you just need a clock to drive another part of your logic in the FPGA, the easy answer is to use a clock enable.

也就是说，将慢速逻辑与其他所有时钟都在相同的（快速）时钟上运行，但我们为此缓慢地启用了。示例：

That is, run your slow logic on the same (fast) clock as everything else, but us a slow enable for it. Example:

signal clk_enable_200kHz  : std_logic;
signal clk_enable_counter : std_logic_vector(9 downto 0);

--Create the clock enable:
process(clk_200MHz)
begin
  if(rising_edge(clk_200MHz)) then
    clk_enable_counter <= clk_enable_counter + 1;
    if(clk_enable_counter = 0) then
      clk_enable_200kHz <= '1';
    else
      clk_enable_200kHz <= '0';
    end if;
  end if;
end process;


--Slow process:
process(clk_200MHz)
begin
  if(rising_edge(clk_200MHz)) then
    if(reset = '1') then
      --Do reset
    elsif(clk_enable_200kHz = '1') then
      --Do stuff
    end if;
  end if;
end process;

虽然200kHz是近似值，但是上述值基本上可以扩展到您需要的任何时钟使能频率。而且，大多数FPGA的FPGA硬件都应该直接支持它（至少在Xilinx部件中才有）。

The 200kHz is approximate though, but the above can be extended to basically any clock enable frequency you need. Also, it should be supported directly by the FPGA hardware in most FPGAs (it is in Xilinx parts at least).

门控时钟几乎总是一个坏主意，因为人们通常会忘记它们正在创建新的时钟域，因此在它们之间连接信号时不会采取必要的预防措施。它还在FPGA内部使用更多的时钟线，因此如果您有很多门控时钟，您可能会很快用完所有可用的线。

Gated clocks are almost always a bad idea, as people often forget that they are creating new clock-domains, and thus do not take the necessary precautions when interfacing signals between these. It also uses more clock-lines inside the FPGA, so you might quickly use up all your available lines if you have a lot of gated clocks.

时钟使能没有任何作用这些弊端。一切都在相同的时钟域中运行（尽管速度不同），因此您可以轻松使用相同的信号，而无需任何同步器或类似设备。

Clock enables have none of these drawbacks. Everything runs in the same clock domain (although at different speeds), so you can easily use the same signals without any synchronizers or similar.

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