驱动输入时钟输出 [英] Drive input clock to output

问题描述

我有一个具有8位输入和串行输出的模块，我想对输入数据进行序列化并将其与时钟同步。

I've a module that have a 8bit input and a serial output, I want to serialize input data and synchronize it with a clock.

我要设置我的数据在下降沿时等待，然后在时钟上升时等待，当时钟再次下降时我设置另一个数据。我不想将直接参考时钟连接到输出，因为当我不使用此模块时，我希望时钟输出为1状态。

I want to set my data when falling edge then wait when clock rise, when clock fall again I set another data. I don't want to connect the directly reference clock to the output because when I don't use this module I want a 1 state on clock output.

我已经尝试了以下代码：

I've tried this code:

process(Clock, ModuleReset)
    begin
        if ModuleReset = '0' then
            OutData <= '0';
            OutCK <= '0';
            counter <= 7;
        elsif falling_edge(Clock) then
                OutCK <= '0';
                OutData <= Data(counter);
        elsif rising_edge(Clock) then
                OutCK <= '1';
        end if;
end process;

合成器给我这个错误：

不支持SCK的非恒定数据的异步加载

"Asynchronous load of non-constant data for SCK is not supported"

当我分离代码时在这样的两个块中：

When I separate the code in two blocks like this:

process(Clock, ModuleReset)
    begin
        if ModuleReset = '0' then
            OutData <= '0';
            OutCK <= '0';
            counter <= 7;
        elsif falling_edge(Clock) then
                OutCK <= '0';
                OutData <= Data(counter);
end process;

process(Clock)
        if rising_edge(Clock) then
                OutCK <= '1';
        end if;
end process;

我有以下两个错误：

净SCK的多个非三态驱动器

净SCK的未解决的三态驱动器

"Multiple non tristate drivers for net SCK"
"Unresolved tristate drivers for net SCK"

我尝试过的另一个代码是：

Another code I've tried is:

process(Clock, ModuleReset)
    if ModuleEN = '1' then
       OutCK <= Clock;
    end if;
    begin
        if ModuleReset = '0' then
            OutData <= '0';
            OutCK <= '0';
            counter <= 7;
        elsif falling_edge(Clock) then
                OutCK <= '0';
                OutData <= Data(counter);
        end if;
end process;

但是输出时钟的频率看起来很奇怪。

But the output clock looks strange with a different frequency.

推荐答案

您认为您的最后一个想法不尽人意。如果您的时钟很慢，那应该没问题，但是我还是建议您修复它。

Your last idea, which I understand ended up working for you, is sub-optimal. If your clock is slow, it should be fine, but I suggest you fix it nevertheless.

if ModuleEN = '1' then
    OutCK <= Clock;
else
    OutCK <= '1';
end if;

产生带有时钟信号的组合逻辑，用于输出。永远不建议将时钟用作逻辑信号，因为时钟使用的时钟路径无法很好地路由到常规路由资源。输出信号将具有潜在的毛刺（对于输出接口来说非常糟糕！）和较大的延迟/偏斜。

Yields combinational logic with the clock signals for the output. Having the clock used as a logic signal is never recommended, since clocks use clock paths which doesn't route well to general routing resources. The output signal will have potential glitches (very bad for an output interface!) and large delay/skew.

您的第一种方法是使用DDR寄存器转发时钟，的确是正确和最佳的方法。使用此方案，您的时钟仅使用时钟路径，并且如果输出时钟和数据的两个寄存器都位于IO块中，它们将具有相同的输出延迟，并且几乎没有偏斜。

Your first approach, to use a DDR register to forward the clock, is indeed the correct and best approach. With this scheme, your clock only use clock paths, and if both the registers outputing the clock and data are situated in IO blocks, they will have the same output delay with very little skew.

您没有指定正在使用的技术，但是我建议您查找如何编写映射到DDR寄存器以用于合成器的代码。另外，您可以手动实例化DDR输出寄存器原语，对于Xilinx可能是ODDR，对于Altera可能是ALTDDIO_OUT。

You didn't specify the technology you're using, but I suggest you lookup how to write code that maps to DDR register for your synthesizer. Alternatively, you can manually instantiate the DDR output register primitive, likely ODDR for Xilinx or ALTDDIO_OUT for altera.

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