当一个实体上有多个架构时会发生什么？ [英] What happens when there are multiple architectures on a single entity?

问题描述

假设一个实体定义了两种架构。这两种体系结构（显然）使用相同的实体，随后两者将输出引脚设置为不同的值。我的问题是，程序（模拟器）如何确定输出应该是什么（即选择哪种架构）？

Suppose one has an entity which has two architectures defined. Those two architectures work with the same entity (obviously) and subsequently the two set the output pins to different values. My question is, how does the program (simulator) determine what the output should be (i.e. which architecture to choose)?

这里有一个例子：

library ieee;
use ieee.std_logic_1164.all;

entity Exercise_4 is 
generic (n : integer := 4);
port(
a, b : std_logic_vector (n-1 downto 0);
clk, rst : std_logic;
q, qn : buffer std_logic_vector (n-1 downto 0));
end;

architecture one of Exercise_4  is
begin
process (clk, rst)
    begin
    if rst = '0' then 
        q <= (others=>'0');
    elsif (clk' event and clk = '0') then
        q <= a ;
    end if;
end process;

process (clk, rst)
begin
    if rst = '0' then 
        qn <= (others=>'1');
    elsif (clk' event and clk = '0') then
        for i in a'range loop
            qn(i) <= not q(i) ;
        end loop;
    end if;
end process;
end;

architecture two of Exercise_4  is
begin
process (clk,rst)
    begin
    if rst = '0' then 
        q <= (others=>'0'); 
        qn <= (others=>'0');
    elsif (clk' event and clk = '0') then
        q <= a;
        qn <= b ;
    end if;
end process;
end;

我做了一个模拟，发现 q 获得分配的 a 的值，而 qn 获得的值 b 已分配。似乎编译器已经选择了第二种体系结构，我不明白为什么程序决定这样做。

I did a simulation and saw that q gets the value of a assigned and qn gets the value of b assigned. It seems that the second architecture has been chosen by the compiler I don't understand why the program decided to do so.

谢谢。

推荐答案

如果您未指定要选择的体系结构²，则编译器将采用与实体声明关联的最新分析体系结构主体（假设编译器符合IEEE标准）[1]。

If you don't specify yourself which architecture to choose² then the compiler will take "the most recently analyzed architecture body associated with the entity declaration" (assuming the compiler is compliant to the IEEE standard) [1].

²您可以选择所需的体系结构，例如在更高的设计级别上的组件声明部分（用于映射信号）中：

² You can select the architecture you prefer e.g. in the component declaration section (where you map the signals) on a higher design level:

entity topentity is 
end;

architecture toparch of topentity is

  -- component instantiation
  component Exercise_4 is
  generic (n : integer := 4);
  port(
    a, b : std_logic_vector (n-1 downto 0);
    clk, rst : std_logic;
    q, qn : buffer std_logic_vector (n-1 downto 0));
  end component Exercise_4;

begin

  -- component mapping
  E4: entity work.Exercise_4(one)
  generic map ( .. )
  port( .. );

end architecture toparch;

[1] IEEE Std 1076-2008 7.3.3默认绑定指示，第4段。

[1] IEEE Std 1076-2008 7.3.3 Default binding indication, paragraph 4.

免责声明：答案是在上述注释的帮助下构造的。无侵犯版权之意。 ; P

Disclaimer: Answer was constructed with the help of the comments above. No copyright infringement intended. ;P

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