最少的D触发器 [英] Minimal number of D flip-flops

问题描述

我遇到了以下问题，不能确定答案。您有任何建议吗，任何帮助将不胜感激。

I have encountered the following question and can't be sure on the answer. Do you have any suggestions, any help would be much appreciated.

斐波那契数列F（n）由F（1）= 1，F（2）= 1和Fn = F（n-2）+ F定义（n-1）对于所有整数n> =3。设计一个计数器电路以输出前七个斐波那契数（即F1至F7）所需的最少D个触发器（连同组合逻辑）是多少？然后环绕？

The Fibonacci sequence F(n) is defined by F(1)=1, F(2)=1, and Fn=F(n-2) + F(n-1) for all integers n>= 3. What is the minimal number of D flip-flops required (along with combinational logic) to design a counter circuit that outputs the first seven Fibonacci numbers (i.e., F1 through F7 ) and then wraps around?

（A）3（B）4（C）5（D）6（E）7

(A) 3 (B) 4 (C) 5 (D) 6 (E) 7

预先感谢

推荐答案

获得7个不同输出所需的最小触发器数量仅为3。但是随后涉及大量组合电路，将七个唯一的输出解码为所需的斐波那契序列。其中一个解码电路使用四个4：1多路复用器，其中每个多路复用器输出代表斐波那契序列的一位。

The minimum number of flipflops required would be only 3 for getting seven different outputs. But then it involves a lot of combinatorial circuitary for decoding the seven unique outputs into the required fibonacci sequence.One of those decoding circuit is using four 4:1 mux where, each mux output represents one bit of the fibonacci sequence.

但是使用4个触发器，我们可以获得一个同步计数器，该计数器仅经过这些状态1,1,2,3,5,8,13并环绕。我认为此过程涉及的巡回过程要少一些。在此应仅将1的出现次数区分两次，这可以通过使用额外的nand门来完成。

But using 4 flipflops we can get a synchronous counter which goes through only these states 1,1,2,3,5,8,13 and wraping around. I think that this process involves a bit less circuitary.Here care should be taken only to differentiate the occurence of 1 twice, which, can be done through the use of an extra nand gate.

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