如果我们总是可以填充延迟时隙，那么就不需要分支预测了吗？ [英] Is that true if we can always fill the delay slot there is no need for branch prediction?

问题描述

我正在研究H& P第三版的MIPS管道的五个阶段（ID，IF，EXE，MEM，WB）。在我看来，分支决定是在ID阶段解决的，因此当分支指令到达其EXE阶段时，分支之后的第二条指令可以正确执行（可以提取）。但这给我们留下了可能仍然在分支指令之后不久浪费第一条指令的问题。

I'm looking at the five stages MIPS pipeline (ID,IF,EXE,MEM,WB) in H&P 3rd ed. and it seems to me that the branch decision is resolved at the stage of ID so that while the branch instruction reaches its EXE stage, the second instruction after the branch can be executed correctly (can be fetched). But this leaves us the problem of possibly still wasting the 1st instruction soon after the branch instruction.

我也遇到了分支延迟槽的概念，这意味着您要填充分支之后的第一条指令具有一些有用的信息，并且无害地表明是否按照需要执行了该指令，并且不会浪费分支后的第一条指令。

I also encountered the concept of branch delay slot, which means you want to fill the 1st instruction soon after the branch with something useful as well as "harmless" that whether the branch is taken or not the instruction is executed as desired and the 1st instruction after the branch is not wasted.

我的问题是，首先，我的上述理解正确吗？如果是正确的话，那么问题就出在分支预测的概念上，分支预测似乎试图用来自程序要去的预测位置的指令来填充第一条指令。但是，如果我们总能找到一些指令来填补分支延迟时隙，那么我们就不需要分支预测功能了，对吗？

My question is, first of all, is my above understanding correct? If it's correct, then the problem comes from the concept of branch prediction, which seems to be trying to fill the first instruction with instruction from the predicted place that the program is going to. But if we can always find some instruction to fill the branch delay slot, we would not need the feature of branch prediction, right?

推荐答案

对于经典的MIPS（R2000）管道，分支延迟时隙使分支预测无用。 （从技术上讲，一种设计可以将延迟时隙指令是否为nop的预测器/指示符与分支预测器相结合。这将跳过该nop，从而适度地提高了正确分支预测的性能。）

For the classic MIPS (R2000) pipeline, the branch delay slot makes branch prediction useless as you perceive. (Technically, a design could combine a predictor/indicator of whether the delay slot instruction is a nop with a branch predictor. This would allow the nop to be skipped, modestly improving performance on a correct branch prediction.)

但是，处理器流水线通常足够长且足够宽（并且分支条件评估已充分延迟），以至于单个延迟槽不足以填补需要分支后指令地址与

However, processor pipelines are often long and wide enough (and branch condition evaluation sufficiently delayed) that a single delay slot is not sufficient to fill the delay between when the post-branch instruction address is needed and the branch direction and target are known.

例如，后续处理器MIPS R4000大大延长了管线，因此无法确定目标位置。分支机构后的指示要足够早。设计人员选择使用一种简单的静态预测不采用的策略。

For example, a follow-on processor, the MIPS R4000, significantly lengthened the pipeline and as a result could not determine the location of the post-branch instruction early enough. The designers chose to use a simple static predict not-taken strategy.

如果不关心二进制兼容性，则可以增加更多的延迟时隙。然而，随着插槽数量的增加，找到有用的指令来填充此类插槽的难度增加。对于某些富含循环的代码，定期填充两个延迟时隙可能是可行的，我认为至少一个DSP具有两个延迟时隙。

If one did not care about binary compatibility, one could add more delay slots. However, finding useful instructions to fill such slots increases in difficulty as the number of slots increases. For certain loop-rich code, regularly filling two delay slots might be practical, and I think at least one DSP had two delay slots.

分支预测还可以用于将取回与执行分离，以便即使无法评估条件（例如，取决于高延迟操作的结果，例如数据高速缓存未命中或除法），取回也可以继续。这样的解耦可用于及早生成指令高速缓存未命中（隐藏其某些延迟），并减少不同阶段可变吞吐量的影响（因此，当较晚阶段停顿或降低吞吐量时，较早阶段可以继续以最大吞吐量运行），并且然后缓冲的指令可以隐藏后面的停顿或降低早期的吞吐量。

Branch prediction can also be used to decouple fetch from execution so that even if the condition cannot be evaluated (e.g., depending on the result of a high latency operation such as a data cache miss or a division), fetch can continue. Such decoupling could be used to generate instruction cache misses early (hiding some of their latency) and to reduce the impact of variable throughput at different stages (so an earlier stage can continue operating with maximum throughput when a later stage stalls or has reduced throughput and the buffered instructions can then hide later stalls or reduced throughput in the earlier stage).

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