跟踪CPU指令重新排序 [英] Trace of CPU Instruction Reordering

问题描述

我研究了一些有关处理器进行指令重排序和Tomasulo算法的事情。

I have studied a few things about instruction re-ordering by processors and Tomasulo's algorithm.

为了更深入地理解这一主题，我想知道是否存在有什么方法（获取跟踪信息）来查看给定程序的实际动态重新排序？

In an attempt to understand this topic bit more I want to know if there is ANY way to (get the trace) see the actual dynamic reordering done for a given program?

我想提供一个输入程序并查看乱序指令执行跟踪。

I want to give an input program and see the "out of order instruction execution trace" of my program.

我可以使用IBM-P7机器和Intel Core2Duo笔记本电脑。还请告诉我是否有一种简单的选择。

I have access to an IBM-P7 machine and an Intel Core2Duo laptop. Also please tell me if there is an easy alternative.

推荐答案

您无权访问CPU内部进行的实际重新排序（有没有公开的启用跟踪的方法）。但是有一些重新排序的仿真器，其中一些可以给您有用的提示。

You have no access to actual reordering done inside the CPU (there is no publically known way to enable tracing). But there is some emulators of reordering and some of them can give you useful hints.

对于现代的Intel CPU（核心2，nehalem，Sandy和Ivy）， （R）架构代码分析器（IACA）。它的主页是 http://software.intel.com/cn -us / articles / intel-architecture-code-analyzer /

For modern Intel CPUs (core 2, nehalem, Sandy and Ivy) there is "Intel(R) Architecture Code Analyzer" (IACA) from Intel. It's homepage is http://software.intel.com/en-us/articles/intel-architecture-code-analyzer/

此工具可让您查看如何将一些线性代码片段拆分为微型代码操作以及如何将其计划到执行端口中。该工具有一些局限性，并且仅仅是CPU u-op重新排序和执行的不精确模型。

This tool allows you to look how some linear fragment of code will be splitted into micro-operations and how they will be planned into execution Ports. This tool has some limitations and it is only inexact model of CPU u-op reordering and execution.

还有一些用于模拟x86 / x86_84 CPU内部的外部工具。 ，我可以推荐 PTLsim （或派生的 MARSSx86 ）：

There are also some "external" tools for emulating x86/x86_84 CPU internals, I can recommend the PTLsim (or derived MARSSx86):

PTLsim对现代超标量进行了建模与x86-64兼容的处理器核心，可配置的详细信息级别，直至所有关键管道结构的RTL级别模型。此外，所有的微代码，完整的缓存层次结构，内存子系统和支持的硬件设备都具有真实的循环精度。

PTLsim models a modern superscalar out of order x86-64 compatible processor core at a configurable level of detail ranging ... down to RTL level models of all key pipeline structures. In addition, all microcode, the complete cache hierarchy, memory subsystem and supporting hardware devices are modeled with true cycle accuracy.

但是PTLsim为某些 PTL cpu建模，而不是真正的AMD或Intel CPU。好消息是，根据想法，此PTL为乱序

But PTLsim models some "PTL" cpu, not real AMD or Intel CPU. The good news is that this PTL is Out-Of-Order, based on ideas from real cores:

此模型的基本微体系结构是Intel Pentium 4，AMD K8和Intel Core 2的设计功能的组合，但结合了IBM Power4 / Power5和Alpha EV8的一些想法。

The basic microarchitecture of this model is a combination of design features from the Intel Pentium 4, AMD K8 and Intel Core 2, but incorporates some ideas from IBM Power4/Power5 and Alpha EV8.

此外，尽管 http://es.cs.uni-kl.de/publications/datarsg/Senf11.pdf 是说 JavaHASE applet 能够模拟不同的简单CPU甚至支持 Tomasulo示例。

Also, in arbeit http://es.cs.uni-kl.de/publications/datarsg/Senf11.pdf is said that JavaHASE applet is capable of emulating different simple CPUs and even supports Tomasulo example.

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