在多线程的情况下，为什么每个逻辑CPU都有自己的CR3寄存器？ [英] Why each logical CPU has it's own CR3 register in case of multithreading?

问题描述

当我们有一个支持某种形式的多线程的CPU时，每个逻辑CPU都有自己的一组寄存器（至少），包括一个CR3寄存器。

When we have a CPU that supports some form of multithreading, each logical CPU has it's own set of registers (as a minimum), including a CR3 register.

由于我们在执行不同的线程时正在处理同一进程的虚拟地址空间，并且永远不会发生上下文切换（切换同一进程的线程时，TLB缓存都不会失效），为什么我们需要一个CR3寄存器来指向

Since we are working on the vitual address space of the same process when executing different threads and a context switch never happens (neither the TLB cache gets invalidated when switching threads of the same process), why do we need a CR3 register to point to the page table and page directory in the logical CPU?

该值不是总是与物理CPU的CR3中的值相同吗？

Isn't the value always the same as the value in the CR3 of the physcial CPU?

推荐答案

由于我们在执行不同线程时正在处理同一进程的虚拟地址空间

Since we are working on the vitual address space of the same process when executing different threads

那不是HT的全部功能。我认为您正在将硬件线程（执行上下文/逻辑核心）与软件线程混淆。

That's not all HT is capable of. I think you're confusing "hardware thread" (execution context / logical core) with "software thread".

两个逻辑核心运行在一个物理核心上，而一个物理核心iTLB / dTLB / L2TLB。 逻辑核心非常独立，不必运行同一进程中的线程。

Two logical cores run on one physical core, with one physical iTLB / dTLB / L2TLB. The logical cores are very much independent, and don't have to be running threads from the same process.

像英特尔HT一样的 SMT 设计：如果操作系统必须谨慎地避免使用不同的页表调度线程

This is a desirable property in an SMT design like Intel's HT: If the OS had to carefully avoid scheduling threads with different page tables onto different logical cores of the same physical core, it would require more synchronization between cores.

到同一物理核心的不同逻辑核心上，将需要更多的同步。带有单独的CR3页表的服务器）可以共享一个TLB，因为条目已用PCID（进程上下文ID）标记。在IIRC中，硬件虚拟化也使用类似（或相同？）的标记，以避免在VM出口或在来宾之间切换时需要TLB刷新。

Two threads of different processes (with separate CR3 page tables) can share one TLB because the entries are tagged with a PCID (process-context ID). IIRC, hardware virtualization also uses similar (or the same?) tagging to avoid needing TLB flushes on VM exits or when switching between guests.

操作系统可以设置PCID（ CR3的低12位），以避免上下文切换中需要TLB刷新，此外，它还允许2个进程同时使用TLB。 Linux是否将x86 CPU的PCID功能用于TLB？如果不是，为什么？（因此，Linux通常不使用PCID，但我认为它用于HT。）

The OS can set a PCID (low 12 bits of CR3) to avoid needing TLB flushes on context switches, and as a bonus enables concurrent TLB usage by 2 processes. Does Linux use x86 CPU's PCID feature for TLB? If not, why? (According to that, Linux doesn't generally use PCID, but I assume it does for HT.)

嗯，我我不确定我的详细信息是否正确，但是实际上，即使两个逻辑核心具有不同的CR3，TLB条目也要进行某种标记以使它们分开。

Hmm, I'm not sure I have the details exactly right, but physically there is some kind of tagging of TLB entries to keep them separate even when the two logical cores have different CR3.

根据 Intel论坛线程，SnB系列CPU静态地划分了iTLB（因此，每个逻辑核心获得一半的条目）。

According to an Intel forum thread, SnB-family CPUs statically partition the iTLB (so each logical core gets half the entries). That automatically solves any sharing problems.

dTLB和L2TLB是竞争性共享的，因此它们确实需要标记。

The dTLB and L2TLB are competitively shared, so they do need tagging.

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