RISC-V：立即编码变体 [英] RISC-V: Immediate Encoding Variants

问题描述

在RISC-V指令集手册（用户级ISA）中，我无法理解第2.3节立即编码变体第11页。

In the RISC-V Instruction Set Manual, User-Level ISA, I couldn't understand section 2.3 Immediate Encoding Variants page 11.

有四种类型的指令格式为R，I，S和U，则有S和U类型的一种变体，分别是SB和UJ，我想表示分行和跳转，如图2.3所示。然后就是RISC-V指令产生的即时类型，如图2.4所示。

There is four types of instruction formats R, I, S, and U, then there is a variants of S and U types which are SB and UJ which I suppose mean Branch and Jump as shown in figure 2.3. Then there is the types of Immediate produced by RISC-V instructions shown in figure 2.4.

所以我的问题是，为什么需要SB和UJ？为什么要用这种方式改组立即数？说由RISC-V指令生成的立即数是什么意思？

So my questions are, why the SB and UJ are needed? and why shuffle the Immediate bits in that way? what does it mean to say "the Immediate produced by RISC-V instructions"? and how are they produced in this manner?

推荐答案

为加快解码速度，基本RISC-V ISA会尽可能每个指令中位于同一位置的重要字段。如您在指令格式表中所见，

To speed up decoding, the base RISC-V ISA puts the most important fields in the same place in every instruction. As you can see in the instruction formats table,

• 主要操作码始终位于0-6位。


• 目标寄存器（如果存在）始终位于7-11位。


• 第一源寄存器（如果存在）始终位于15-19位。


• 第二个源寄存器（如果存在）始终位于20-24位。

• The major opcode is always in bits 0-6.
• The destination register, when present, is always in bits 7-11.
• The first source register, when present, is always in bits 15-19.
• The second source register, when present, is always in bits 20-24.

其他位为用于次指令的操作码或其他数据（第12-14位的 funct3 和第25位的 funct7 31），并立即执行。可用于立即数的位数取决于指令中存在的寄存器编号：

The other bits are used for the minor opcode or other data for the instruction (funct3 in bits 12-14 and funct7 in bits 25-31), and for the immediate. How many bits can be used for the immediate depends on how many register numbers are present in the instruction:

• 具有一个目标和两个源的指令寄存器（R型）没有立即数，例如添加两个寄存器（ ADD ）;


• 具有一个目标和一个源的指令寄存器（I型）的立即数有12位，例如，将一个寄存器与立即数（ ADDI ）相加；


• 指令具有两个源寄存器而没有目标寄存器（S型）（例如存储指令）的立即数也有12位，但是它们必须位于不同的位置，因为寄存器号也位于不同的位置；


• 最后，只有目标寄存器而没有次要操作码（U型）的指令，例如 LUI ，可以将20位用于立即操作（主要操作码和目标寄存器号总共需要12位）。

• Instructions with one destination and two source registers (R-type) have no immediate, for instance adding two registers (ADD);
• Instructions with one destination and one source register (I-type) have 12 bits for the immediate, for instance adding one register with an immediate (ADDI);
• Instructions with two source registers and no destination register (S-type), for instance the store instructions, have also 12 bits for the immediate, but they have to be in a different place since the register numbers are also in a different place;
• Finally, instructions with only a destination register and no minor opcode (U-type), for instance LUI, can use 20 bits for the immediate (the major opcode and the destination register number together need 12 bits).

现在从另一个角度考虑将使用这些立即值的指令。 I-immediate和S-immediate这两个最简单的用户仅需要符号扩展的12位值。 U-inmediate指令需要32位值的高20位立即数。最后，由于RISC-V指令始终与偶数地址对齐，因此分支/跳转指令需要在值的低位立即进行符号扩展，最低位始终为零。

Now think from the other point of view, of the instructions which will use these immediate values. The simplest users, I-immediate and S-immediate, need only a sign-extended 12-bit value. The U-immediate instructions need the immediate in the upper 20 bits of a 32-bit value. Finally, the branch/jump instructions need the sign-extended immediate in the lower bits of the value, except for the lowest bit which will always be zero, since RISC-V instructions are always aligned to even addresses.

但是为什么立即位被洗掉了？这次考虑一下解码立即场的物理电路。由于是硬件实现，因此这些位将被并行解码；输出立即数中的每个位都有一个多路复用器来选择它来自哪个输入位。

But why are the immediate bits shuffled? Think this time about the physical circuit which decodes the immediate field. Since it's a hardware implementation, the bits will be decoded in parallel; each bit in the output immediate will have a multiplexer to select which input bit it comes from. The bigger the multiplexer, the costlier and slower it is.

因此，指令编码中立即数的改组是使每个输出立即数具有尽可能少的输入指令位选项。例如，立即数位1只能来自指令位8（S-立即或B-立即），21（I-立即或J-立即）或常数零（U-立即或R型指令，没有立即数） ）。立即数0可以来自指令位7（S-立即），20（I-立即）或常数零。立即数5只能来自指令位25或常数零。

The "shuffling" of the immediate bits in the instruction encoding, therefore, is to make each output immediate bit have as little input instruction bit options as possible. For instance, immediate bit 1 can only come from instruction bits 8 (S-immediate or B-immediate), 21 (I-immediate or J-immediate), or constant zero (U-immediate or R-type instruction which has no immediate). Immediate bit 0 can come from instruction bits 7 (S-immediate), 20 (I-immediate), or constant zero. Immediate bit 5 can only come from instruction bit 25 or constant zero. And so on.

指令位31是一种特殊情况：对于RV-64，立即数的位32-63始终是指令位31的副本。 -out会增加一个延迟，如果还需要一个多路复用器，则延迟会更大，因此它只有一个选项（常数零除外，可以通过忽略整个立即数在管道中稍后对其进行处理）。

Instruction bit 31 is a special case: for RV-64, bits 32-63 of the immediate are always copies of instruction bit 31. This high fan-out adds a delay, which would be even bigger if it also needed a multiplexer, so it only has one option (other than constant zero, which can be treated later in the pipeline by ignoring the whole immediate).

有趣的是，仅主要的操作码（位0-6）才需要知道如何解码立即数，因此立即解码可以与解码其余部分并行进行

It's also interesting to note that only the major opcode (bits 0-6) is needed to know how to decode the immediate, so immediate decoding can be done in parallel with decoding the rest of the instruction.

因此，回答以下问题：

• SB类型使分支范围加倍，因为指令始终与偶数地址对齐；


• UJ类型的总体指令格式与U类型相同，但是立即值位于低位而不是高位；


• 对立即位进行混洗以降低解码成本立即值，方法是减少每个输出立即位的选择数量；


• RISC-V指令产生的立即数表显示了可以从中解码的不同类型的立即值一条RISC-V指令，以及该指令中的每个位来自何处；


• 对于每个输出立即数，使用主操作码（0-6位）将它们生成为：选择了输入指令位。

• SB-type doubles the range of branches, since instructions are always aligned to even addresses;
• UJ-type has the same overall instruction format as U-type, but the immediate value is in the lower bits instead of the upper bits;
• The immediate bits are shuffled to reduce the cost of decoding the immediate value, by reducing the number of choices for each output immediate bit;
• The "immediate produced by RISC-V instructions" table shows the different kinds of immediate values which can be decoded from a RISC-V instruction, and from where in the instruction each bit comes from;
• They are produced by, for each output immediate bit, using the major opcode (bits 0-6) to chose an input instruction bit.

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