用负项乘以幂级数求和 [英] Multiplication by power series summation with negative terms
问题描述
如何在Verilog中计算浮点被乘数?到目前为止，我通常使用shift<< 1024，然后浮点数变为整数.然后，我进行一些操作，然后>> 1024再次获得分数.
How can I calculate a floating point multiplicand in Verilog? So far, I usually use shift << 1024 , then floating point number become to integer. Then I do some operations, then >> 1024 to obtain a fraction again.
例如0.3545 = 2 ^ -2 + 2 ^ -4 + ...
For example 0.3545 = 2^-2 + 2^-4 + ...
我对这样的另一种方式有疑问.我不知道减号(-)的来源:
I have question about another way, like this. I don't know where does the minus (-) comes from:
我刚从某人那里看过这个.但是按照您的方式，它就是这样表示的
I have just look this from someone. but as you way, that is represented like this
我不知道怎么知道减号被使用了吗?
I don't understand how does it know the minus is used it?
我们怎么知道什么时候需要减号?另外我该如何申请Verilog RTL?
How do we know when the minus needed to it? Also how can I apply to verilog RTL?
更新:我理解在操作中使用减号的概念.但是，是否还有其他方法可以使方程式或方法简化表达式乘以2的幂?
UPDATE : I understand the concept the using minus in operation. But Is there any other way to equation or methodologies what to make reduce expression what multiplying with power of 2?
更新:我们如何在verilog中使用此方法?例如，我已经倾斜0.46194 = 2 ^ -1-2 ^ -5-2 ^ -7 + 2 ^ -10.然后这段代码是用verilog这样写的. 0.011101101 ='hED ='d237.因此，问题的关键是我们如何将其应用于verilog中的应用程序?
UPDATE : how can we use this method in verilog? for example, I have leaned 0.46194 = 2^-1 - 2^-5 - 2^-7 + 2^-10. then this code was written like this in verilog. 0.011101101 ='hED = 'd237. So the point of the question is how can we apply it to application in verilog?
更新:先生，您能检查一下吗?结果略有不同.
UPDATE : Sir Would you please check this one? there are a little difference result.
有些不同.我怎么了?
推荐答案
以2为基数的4位数字可以具有以下值:
In a 4 bit base 2 number can have these values:
Base 2: Unsigned 4 bit integer,
2^3 2^2 2^1 2^0
8 4 2 1
如果我们有一个0111，它表示7.如果我们使用移位加法乘以该数字，则将需要3个时钟周期(3个移位和加法).
If we have a 0111 it represents 7. If we were to multiply by this number using a shift add architecture it would take 3 clockcycles (3 shift and adds).
对此的优化称为 CSD(规范签名数字).它允许负一到出现在二进制数字"中.我们将-1表示为一个小节，或者将 T 表示为顶部的小节.
An optimisation to this is called CSD (Canonical Signed Digit. It allows minus one to be present in the 'binary numbers'. We shall represent -1 as one bar, or T as that looks like a one with a bar over the top.
100T表示8 - 1，与0111相同.可以观察到，可以将长距离的1替换为0，以使距离结束而变为1，并且将路径的第一个1变为-1(T).
100T represents 8 - 1 which is the same as 0111. It can be observed that long runs of 1's can be replaced with a the 0 that ends the run becoming 1 and the first 1 of the run becoming a -1, (T).
转换示例:
00111101111
01000T1000T
但是如果在两部分中通过，我们将得到:
But if passed in two section we would get :
00111101111
0011111000T
010000T000T
我们采用一个需要8个时钟周期或8个逻辑块进行计算的数字，并将其转换为3.
We have taken a number that would take 8 clock cycles or 8 blocks of logic to compute and turned it into 3.
与Verilog中的定点值有关的问题 x精确二进制定点表示形式?和verilog-floating-points-multiplication .
Related questions to fixed point values in Verilog x precision binary fixed point representation? and verilog-floating-points-multiplication.
回答有关您有关CSD转换的问题的后续部分.我将它们视为纯整数以简化数字，这与将值乘以2 ^ 9(9个小数位)相同.
To answer the follow up section about your question on CSD conversion. I will look at them as pure integers to simplify the numbers, this is the same as multiplying the values by 2^9 (9 fractional bits).
256 128 64 32 16 8 4 2 1
0 1 1 1 0 1 1 0 1
128 + 64 +32 + 8 +4 +1 => 237
现在进行CSD转换:
256 128 64 32 16 8 4 2 1
1 0 0 T 1 0 T 0 1
256 -32 + 16 - 4 + 1 => 237
您可以看到您的转换是正确的.我得到的237 * 2 ^ -9为0.462890625，当转换回小数时，它与您的答案匹配.开始的0.46194必须是舍入的版本，或者量化为9个小数位时会被截断.该误差称为量化误差.不过，最重要的是您正确地进行了CSD转换.
You can see your conversion was correct. I get 237* 2^-9 as 0.462890625, which matches your answer when converted back to fractional. The 0.46194 that you started with must have been a rounded version, or when quantised to 9 fractional bits gets truncated. This error is known as quantisation error. The most important thing here though is that you got the CSD conversion correct.
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