在Verilog中访问寄存器值 [英] Accessing register values in verilog

问题描述

我初始化寄存器

reg[1:0] yreg;

并对其进行一些操作，即从上一步获得的值.当我在0点添加新值时，程序的迭代将移至1点

and manipulate it a bit, i.e., value from prev. iteration of program is shifted to 1 spot when I add in the new value in the 0 spot

yreg = SIGNAL; //here SIGNAL is an input to the program

然后我想稍后访问寄存器中0和1点的值以进行计算.我怎样才能做到这一点?我最初的反应是yreg[0]和yreg[1](我通常使用python =编程)，但这会产生错误(第35行是其中包含yreg[0]和yreg[1]的代码行):

And then I want to access the values at the 0 and 1 spots in the register later for a calculation. How can I do this? My initial reaction was yreg[0] and yreg[1] (I normally program in python =) but this is producing an error (line 35 is the line of code that has yreg[0] and yreg[1] in it):

ERROR:HDLCompiler:806 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 35: Syntax error near "[".

当我看到这时，我的假设是使用括号访问寄存器的某个索引不是正确的语法.您如何正确访问寄存器索引中的信息?我在查找有关此信息时遇到麻烦.

My assumption when I saw this was that it's not the right syntax to use the brackets to access a certain index of the register. How do you properly access the information in an index of a register? I'm having trouble finding information on this.

很抱歉，这可能是一个荒谬的问题，这是我第一次使用Verilog或FPGA.

Sorry for the probably ridiculous question, this is my first time ever using verilog or FPGAs in general.

module trapverilog(
    input CLK,
    input SIGNAL,
     input x,
    output OUT
    );

reg[1:0] yreg;
float sum = 0;

always @(posedge CLK)
begin
    yreg = SIGNAL; //should shift automatically...?
    sum = ((reg[0] + reg[1])*x/2) + sum; //this is effectively trapezoidal integration
    OUT = sum;
end

endmodule

推荐答案

您对Verilog信号的工作方式有基本的误解.

You have a fundamental misunderstanding of how Verilog signals work.

默认情况下，所有Verilog信号均为单个位.例如，在您的代码中，SIGNAL，x和out都只有一位宽.他们不能存储数字(0或1除外).

By default, all Verilog signals are single bits. For example, in your code, SIGNAL, x, and out are all one bit wide. They cannot store a number (other than 0 or 1).

在定义信号时指定宽度(例如reg [1:0] yreg)可控制使用多少位来表示该信号.例如，yreg是一个两位信号.这并不意味着它自动移位"；而是它只是意味着信号是两位宽的，因此它可以用来表示0到3(除其他外)的数字.

Specifying a width when you define a signal (like reg [1:0] yreg) controls how many bits are used to represent that signal. For instance, yreg is a two-bit signal. This does not mean that it "shifts automatically"; it just means that the signal is two bits wide, allowing it to be used to represent numbers from 0 to 3 (among other things).

我强烈建议您完成数字电子设计课程. Verilog编程与程序编程语言(例如Python)有很大的不同，并且如果不对您在此处实际构建的内容有深入的了解，您将很难理解它.

I would strongly advise that you work through a course in digital electronics design. Verilog programming is very different from procedural programming languages (such as Python), and you will have a hard time making sense of it without a solid understanding of what you are actually building here.

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