ModelSim-模拟按钮按下 [英] ModelSim - Simulating Button Presses

问题描述

我想使用四个按钮作为输入，并使用三个七段LED显示器作为输出.两个按钮应在16个RAM位置中上下移动；其他两个应增加和减少当前显示的存储位置的内容.我现在正在尝试使用ModelSim测试台和按钮按下来模拟我的设计.我认为这是我代码的相关部分:

I want to use four push buttons as inputs and three seven-segment LED displays as outputs. Two push buttons should step up and down through the sixteen RAM locations; the other two should increment and decrement the contents of the currently-displayed memory location. I am now trying to simulate my design using ModelSim test benches, with button presses. Here is what I believe to be the relevant portions of my code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity DE2_TOP is

  port (
    KEY : in std_logic_vector(3 downto 0);         -- Push button
    );

end DE2_TOP;

architecture datapath of DE2_TOP is

begin  
  U1: entity work.lab1 port map (
    key => key,         
  );

end datapath;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity raminfr is                     -STANDARD RAM INFERENCE
    port (
        clk : in std_logic;
        we : in std_logic;
        a : in unsigned(3 downto 0);
        di : in unsigned(7 downto 0);
        do : out unsigned(7 downto 0)
    );
end raminfr;

architecture rtl of raminfr is

type ram_type is array (0 to 15) of unsigned(7 downto 0);
signal RAM : ram_type;
signal read_a : unsigned(3 downto 0);
begin
process (clk)
begin
    if rising_edge(clk) then
        if we = '1' then
            RAM(to_integer(a)) <= di;
        end if;
        read_a <= a;
    end if;
end process;
do <= RAM(to_integer(read_a));
end rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lab1 is
    port(
        clock : in std_logic;
        key : in std_logic_vector(3 downto 0); 
        );
end lab1;

architecture up_and_down of lab1 is
    signal value_in_ram : unsigned(7 downto 0);
    signal clk : std_logic;
    signal we : std_logic;
    signal value_counter    : unsigned(7 downto 0) ;
    signal register_counter : unsigned(3 downto 0);
        begin
    U1: entity work.raminfr port map (
        a   => register_counter,
        di  => value_counter,
        do  => value_in_ram,
        clk => clk,
        we  => we
    );

    process(clock)
        begin
            if rising_edge(clock) then
                if (key(3)='0' and key(2)='0' and key(1)='1' and key(0)='0') then
                    value_counter <= value_counter + "1";   
                elsif (key(3)='0' and key(2)='0' and key(1)='0' and key(0)='1') then  
                    value_counter <= value_counter - "1";   
                elsif (key(3)='1' and key(2)='0' and key(1)='0' and key(0)='0') then
                    register_counter<= register_counter + "1";
                    value_counter <= value_in_ram;
                elsif (key(3)='0' and key(2)='1' and key(1)='0' and key(0)='0') then
                    register_counter<= register_counter - "1";
                    value_counter <= value_in_ram;
                end if;
            end if;
    end process;
end architecture up_and_down;

问题是，尽管在测试台中初始化了键"(按钮)，ModelSim仍将对象列为"UUUU".这是我的测试平台的代码，位于单独的文件中:

The problem is that despite initializing "key" (the buttons) in my test bench, ModelSim still lists the object as "UUUU". Here is the code for my test bench, which is located in a separate file:

library ieee;
use ieee.std_logic_1164.all;

entity DE2_TOP_TEST is
end;

architecture BENCH of DE2_TOP_TEST is
signal KEY : std_logic_vector(3 downto 0);

begin
    KEY<="0010";
    U1: entity work.DE2_TOP port map (
        key=>key,
    );
end BENCH;

有人知道怎么了吗?

推荐答案

在设计中使用寄存器.因此，您需要在时钟输入中添加一个信号:

You use registers in your design. So you need to add a signal to your clock input:

constant tb_clk_period : time       := (1 sec) / 10_000_000; -- 10 MHz
signal   tb_clk        : std_ulogic := '0';
...
-- clock generator
tb_clk <= not tb_clk after tb_clk_period / 2;

这篇关于ModelSim-模拟按钮按下的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！