如何从VHDL内部架构写入两个输出端口? [英] How to write to two output ports from inside architecture in VHDL?

问题描述

在尝试将组件连接到VHDL中父级层次结构的两个输出端口时遇到问题.由于只能通过端口映射"语句完成物理连接，因此无法将本地信号连接到多个输出端口.这是一个示例:

I encountered a problem when trying to connect a component to two output ports of parent hierarchy in VHDL. Since the physical connection can be done only via "port map" statement, there is no way to connect local signal to more than one output port. Here is an example:

以上电路的描述应简短.像这样:

The description of the above circuit should be smth. like this:

entity HIER is
port (
    IN1 : in bit;
    OUT1, OUT2 : out bit);
end hier;

architecture HIER_IMPL of HIER is 
   component BUF is 
      port (a : in bit; o : out bit);
   end component;
begin
   BUF1 : BUF port map (a => IN1, o => OUT1, o => OUT2);
end HIER_IMPL;

但是，由于VHDL禁止将输出端口"o"同时分配给OUT1和OUT2，因此无法正常工作.

However, double assignment of output port "o" to both OUT1 and OUT2 won't work as it is prohibited in VHDL.

推荐答案

是否存在无法创建内部信号并不能使用该信号来驱动两个输出端口的原因?

Is there a reason why you cannot create an internal signal and use that signal to drive the two output ports like this?

entity HIER is
port (
    IN1 : in bit;
    OUT1, OUT2 : out bit);
end hier;

architecture HIER_IMPL of HIER is 
   signal temp : bit;
   component BUF is 
      port (a : in bit; o : out bit);
   end component;
begin
   BUF1 : BUF port map (a => IN1, o => temp);
   OUT1 <= temp;
   OUT2 <= temp;

end HIER_IMPL;

如果这不可能，那怎么办?

If this is not possible, how about this?

entity HIER is
port (
    IN1 : in bit;
    OUT1, OUT2 : out bit);
end hier;

architecture HIER_IMPL of HIER is 
   component BUF is 
      port (a : in bit; o : out bit);
   end component;
begin
   BUF1 : BUF port map (a => IN1, o => OUT1);
   BUF2 : BUF port map (a => IN1, o => OUT2);
end HIER_IMPL;

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