Inte CPU的微体系结构中的快速LEA和慢速LEA单元是什么? [英] What are fast LEA and slow LEA unit in the microarchitecture of Inte's CPU?

问题描述

我从下面的链接中看到haswell的微体系结构，其中提到一些管道可以进行快速LEA，而某些管道可以运行慢速LEA，那么这里的快速LEA和慢速LEA是什么意思?与LEA指令有关吗?搜索结果通常偏向LEA指令，不会导致直接答案.

I saw haswell's microarchitecture from below link mentioned that some pipelines can carry on fast LEA and some can run slow LEA, what's the meaning of fast LEA and slow LEA here? Related to LEA instruction? The search results are usually biases to LEA instruction, and don't lead to direct answer.

http://www.realworldtech.com/haswell-cpu/4/

推荐答案

大多数专用ALU单元仅存在于部分执行端口上(代代之间不断进行更改)，CPU必须选择一种可能的方式.根据正在执行的指令(或更确切地说是微操作)进行端口切换.当多个相同的端口可以执行相同操作时，应尝试进行一些平衡，并且可能还有其他可能的因素.当然，确切的算法永远不会发布.

Most dedicated ALU units exist only on part of the execution ports (with constant changes being made from generation to generation), the CPU has to pick one of the possible ports according to the instruction (or rather the micro-operation) being performed. When Multiple identical ports can do the same, it should attempt to do some balancing, and there may be other possible factors. The exact algorithm of course is never published.

但是，根据

In this case however, the LEA operations are split into slow and fast ones, according to this link, the slow ones are due to using 3 operand LEAs (base, index, offset). It actually also provides you with a performance monitor to measure how many such cases you encounter.

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