在Intel Core i3/i7的情况下,数据从缓存中逐出后的位置 [英] Where data goes after Eviction from cache set in case of Intel Core i3/i7

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本文介绍了在Intel Core i3/i7的情况下,数据从缓存中逐出后的位置的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!

问题描述

L1/L2高速缓存包含在Intel中,L1/L2高速缓存具有8种方式的关联性,意味着在一组中存在8条不同的高速缓存行.缓存行是整体操作的,这意味着如果我想从缓存行中删除一些字节,则整个缓存行都将被删除,而不仅仅是我要删除的那些字节.我说的对吗?

The L1/L2 cache are inclusive in Intel and L1 / L2 cache is 8 way associativity, means in a set there are 8 different cache lines exist. The cache lines are operated as a whole, means if I want to remove few bytes from a cache line, the whole cache line will be removed , not the only those bytes which I want to remove. Am I right ?

现在,我的问题是,无论何时通过某种其他过程或使用clflush(手动逐出高速缓存行/块)从高速缓存中移除/逐出集合的高速缓存行时,系统是否会存储逐出的该高速缓存行中某个位置(在任何缓冲区,寄存器等中)的数据,以便与从主内存或更高级别的高速缓存中加载数据相比,下次可以从该位置加载数据以减少延迟, ,它总是使缓存中的数据无效,并在下一次从下一个更高级别加载数据.

Now, my question is whenever a cache line of a set is removed/evicted from cache, either by some other process or by using clflush(manual eviction of a cache line/block ), does system store the evicted data of that cache line somewhere (in any buffer, register etc), so that next time it can load the data from that place to reduce the latency as compared to loading the data from main memory or higher level of cache, OR it ALWAYS simply invalidate the data in cache and next time loaded the data from next higher level.

对于本文的任何建议或任何链接,我们将不胜感激.提前致谢.

Any suggestion or any link for the article will be highly appreciated. Thanks in advance.

推荐答案

L1/L2不一定包含所有内容,只有最后一级的缓存是已知的,在i7上将是L3. 您说对了,高速缓存行是基本的高速缓存元素,您必须正确抛出整个高速缓存行才能填充新的高速缓存行(或使该单行无效时).您可以在此处了解更多相关信息- http://www.tomshardware.com/reviews/Intel-i7-nehalem-cpu,2041-10.html

L1/L2 are not necessarily inclusive, only the last-level cache is known to be so, which on i7 would be the L3. You are right in saying that a cache line is the basic caching element, you would have to throw a whole cacheline in order to fill in a new one (or when invalidating that single line). You can read some more about that here - http://www.tomshardware.com/reviews/Intel-i7-nehalem-cpu,2041-10.html

当删除一行时,所采取的措施取决于其MESI状态(MESI及其派生是用于高速缓存一致性维护的协议).如果修改了该行("M"),则必须将数据写回"到下一级缓存(如果未命中,它可能会分配到该缓存,或者直写"到下一个缓存-取决于缓存所维护的策略).请注意,当到达最后一级缓存时,您将必须命中它(包括端值).从最后一级的缓存中逐出一行时-必须将其写入内存.无论哪种方式,未能写回修改后的行都会导致失去一致性,这很可能会导致执行不正确.

When a line is removed, the action taken depends on its MESI state (MESI and its derivatives are the protocols for cache coherency maintenance). If the line if modified, ("M") then the data must be "written-back" to the next level cache (in case of a miss it may allocate there, or "write-through" on to the next level - depends on the policy that cache maintains). Note that when you reach the last level cache you would have to hit as it's inclusive. When evicting a line from the last level cache - it would have to get written to the memory. Either way, failing to write back a modified line would result in loss of coherency, which would most likely result in incorrect execution.

如果未修改该行(无效,互斥或共享),则CPU可以静默删除该行而无需回写,从而节省了带宽.顺便说一下,在更复杂的缓存协议(例如MESIF或MOESI)中,还有其他几种状态.

If the line is not modified (Invalid, Exclusive or Shared), than the CPU may silently drop it without need of writeback, thereby saving bandwidth. By the way, there are also several other states in more complicated cache protocols (like MESIF or MOESI).

通过搜索缓存一致性协议",您可以找到很多解释.如果您希望使用更可靠的资源,则可以参考任何CPU体系结构或缓存设计教科书,我个人推荐Hennessy& Patterson的计算机体系结构,一种定量方法",其中有整整一章关于缓存性能,但是这里有点题外话了.

You can find lots of explanations by googling for "cache coherence protocols". If you prefer a more solid source, you can refer to any CPU architecture or cache design textbook, I personally recommend Hennessy&Patterson's "Computer Architecture, a quantitative approach", there's a whole chapter on cache performance, but that's a bit off topic here.

小更新:从Skylake开始,某些CPU(服务器段)不再具有包含L3,而是具有非包含L3(以支持增加的L2).这意味着当L2老化后,干净的行也有可能被写回,因为L3通常不保存它们的副本.

Small update: as of Skylake, some of the CPUs (server segments) no longer have an inclusive L3, but rather a non-inclusive (to support an increased L2). This means that clean lines are also likely to get written back when aging out of the L2, since the L3 does not normally hold copies of them.

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