更改TTB_BASE的更好方法? [英] the better way to change TTB_BASE?

问题描述

关闭/打开mmu并不是在ARM中切换TTB_BASE的好方法.那么更好的方法是什么呢?主要步骤是这样的吗?(ARM 920T ARMV4T)

turning off/on mmu is not a good way to switch TTB_BASE in ARM as far as I know .So what is the better way ? Is the main steps like this ? (ARM 920T ARMV4T)

1.同步dcache->外部存储器
2.clean_icache()&&invalidate_dcache();//这是我的问题，如果当前指令在icache中存在，则我要清理&使它们失效，ARM内核如何知道下一步是什么?ARM内核可以再次从外部存储器中获取指令吗?
3.使整个tlb失效
4.更改ttb基址寄存器

1 . sync dcache --> external memory
2 . clean_icache () && invalidate_dcache () ; // this is my question ,if the current instruction alreay in icache ,then I clean & invalidate them ,how can ARM core knows what is the next step ? May ARM core fetch instructions from external memory again ?
3. invalidate whole tlb
4. change the ttb base register

还有另一种更好的方法吗?任何帮助表示赞赏！^ _ ^

Is there another better way ? Any help appreciated ! ^_^

推荐答案

切换 TTB_BASE 与打开MMU几乎相同.在操作之前，有一个存储空间，在后面有另一个存储空间.您需要当前执行的代码以在操作期间保持有效.选择是

Switching the TTB_BASE is much the same as turning on the MMU. Before the operation, there is one memory space and after there is another. You need your currently executing code to remain valid during the operation. Choices are,

1. 将当前代码映射到两者中的相同位置.
2. 依靠缓存进行过渡.

启用MMU时，1 ^st 基本上与 phys == virt 相同.更新 TTB_BASE 时，最基本的是完整版本的完整副本.如果中断被锁定，则您可能只需要映射切换代码所需的页面.这可能是两阶段操作，其中当前代码页最终会重新定位到其他某个内存地址.首先 页面， branch 到 alias 位置，然后删除 original 页面.在每个步骤中，都安全地刷新 TLB 和缓存.您可能不需要执行此操作，具体取决于更改的上下文.但是，在第一次 flush 之后，对于 d-cache ， i-cache 和 TLB而言，后续后续刷新并不昂贵.

The 1^st is basically with phys == virt when enabling the MMU. When updating the TTB_BASE a complete copy of the old version is the most basic. If interrupts are locked, you may only need to map pages needed by the switching code. This maybe a two phase operation where the current code page is eventually re-located to some other memory address. First alias the page, branch to the alias location and remove the original page. At every step, it is safe to flush the TLB and caches. You may not need to do this, depending on the context of the change. However, after the first flush, sub-sequent flushes are not expensive for each of d-cache, i-cache and TLB.

2 ^nd 方法相当简单.在 StrongARM 上，当启用MMU时，这被称为死亡之舞.基本上，对指令进行计时，以便预取和 NOP 填充将对指令进行排序，以便从 phys 地址到 virt 地址在过渡时就可以使用.为了更新 TTB_BASE ，您可以假设当前代码页位于TLB中，并且如果代码正确对齐 ，则会启动 I-CACHE 行.在 TTB_BASE 更新之后，大约有六条指令可以在CPU提取任何内存之前执行.如果您不刷新 TLB ，则它是一个整页.

The 2^nd method is rather flakey. On the StrongARM, this was known as the dance of death, when enabling the MMU. Basically, the instructions where timed so that prefetching and NOP padding would sequence the instructions so that a branch was performed from the phys address to the virt address right at the time of transition. For updating the TTB_BASE, you can assume that the current code page is in the TLB and if the code is aligned properly it starts an I-CACHE line. There are about six instructions that maybe performed after the TTB_BASE update before any memory will be fetched by the CPU. It is a full page, if you don't flush the TLB.

我只能看到在 hypervisor 想要频繁切换整个内存映射的情况下使用的2 ^nd 方法.通常，管理程序只会在上下文切换上更改内存映射的一部分.2 ^nd 方法稍快一些，但缺点很明显.

I can only see the 2^nd method being used in the case of a hypervisor that wants to switch an entire memory map frequently; generally hypervisors will only change part of the memory map on a context switch. The 2^nd method is slightly faster, but the down sides should be obvious.

这篇关于更改TTB_BASE的更好方法?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！