缓存块标签大小 [英] Cache block tag size

问题描述

我正在使用gcc作为编译器在linux上用C编写一个缓存模拟程序，并且在大多数情况下我已经完成了.只有少数测试用例出错(在应击中的数千个联邦地址中，有些东西丢失了).我在命令行上指定了缓存属性.我怀疑代码中的错误与标记有关(如果事情没有实现，那么它们的标记在应有的情况下就不会匹配).所以我的问题是:我计算标签正确吗?

I'm writing a cache simulation program in C on linux using gcc as the compiler and I'm done for the most part. Only a few test cases go wrong (a few things out of the thousands of fed addresses that should be hitting are missing). I specify the cache properties on the command line. I suspect the error within my code has to do with the tag (if things aren't hitting then their tags aren't matching up when they should be). So my question is: Am I calculating the tag right?

//setting sizes of bits
int offsetSize = log2(lineSize);
int indexSize = 0;
if (strcmp(associativity,"direct") == 0){//direct associativity
  indexSize = log2(numLines);
}else if (assocNum == numLines){//fully associative
  indexSize = 0;
}else{//set associative
  indexSize = log2(assocNum);
}

address = (int) strtol(readAddress,&eptr,16);
unsigned long long int mask = 0;

//get the offset Bits
mask = (1 << offsetSize) - 1;
offsetBits = address & mask;

//get the index bits
mask = (1 << (indexSize)) - 1;
mask = mask << offsetSize;
indexBits = (address & mask) >> offsetSize;

//get tag bits
tagBits = address >> (offsetSize+indexSize);

要馈送的地址通常为48位，因此变量address和mask的类型为unsigned long long int.我认为我遇到的问题是，当我只应该从大地址中取出一小部分位时，我正在占用地址的所有高位字节.

The addresses that are being fed are usually 48 bits, so the variables address and mask is of type unsigned long long int. I think the problem I'm having is that I'm taking all the upper bits of the address, when I should only be taking a small set of bits from the large address.

例如:我在4路组关联缓存中有32个缓存行，块大小为4.

For example: I have 32 cache lines in a 4-way set associative cache with a block size of 4.

offsetSize = log2(4)= 2

offsetSize = log2(4) = 2

indexSize = log2(4)= 2

indexSize = log2(4) = 2

无论地址大小如何，我的代码当前都占用地址的高位，减去最后4位.我应该只使用高28位吗?(tagSize =(8 * 4)-3-2)

My code currently takes the upper bits of the address no matter the address size, minus the last 4 bits. Should I be taking only the upper 28 bits instead? (tagSize = (8*4)-3-2)

推荐答案

无论地址大小如何，我的代码当前都占用地址的高位，减去最后4位.我应该只使用高28位吗?

My code currently takes the upper bits of the address no matter the address size, minus the last 4 bits. Should I be taking only the upper 28 bits instead?

标签必须包含所有高位，以便可以使用标签来确定它是否是缓存命中.

The tag has to contain all upper bits so that the tag can be used to determine if it is or isn't a cache hit.

如果地址是48位并且分为3个字段，则您将有一个2位的高速缓存行中的偏移量"字段，一个2位的高速缓存中的索引"字段和一个44位的高位"字段必须存储在标签"字段中的标签.如果您仅在标记中存储28位，那么当您应该遇到高速缓存未命中时会遇到高速缓存命中(因为高速缓存中的条目恰好包含28位恰好匹配的其他地址的数据).

If addresses are 48-bits and are split into 3 fields, you'd have a 2-bit "offset in cache line" field, a 2-bit "index in cache" field and a 44-bit "upper bits that have to be stored in the tag" field. If you only store 28 bits in the tag then you get cache hits when you should get cache misses (because the entry in the cache happens to contain data for a different address where the 28 bits happened to match).

请注意，您可以/应该将关联性"理解为并行运行的高速缓存行的数量(其中直接映射的只是"associativity = 1"，而完全关联的只是"associativity = total_cache_size"/cache_line_size").关联性对索引大小没有直接影响(仅高速缓存行集的大小与索引大小有关)，而您遇到的问题可能与 indexSize = log2(assocNum); (没有任何意义).

Note that you can/should think of "associativity" as the number of sets of cache lines that happen to operate in parallel (where direct mapped is just "associativity = 1", and where fully associative is just "associativity = total_cache_size / cache_line_size"). The associativity has no direct effect on the index size (only the size of the sets of cache lines matters for index size), and the problem you're having is probably related to indexSize = log2(assocNum); (which doesn't make sense).

换句话说:

    if( direct_mapped ) {
        associativity = 1;
    } else {
        max_associativity = total_cache_size / cache_line_size;
        if( fully_associative || (associativity > max_associativity) ) {
            associativity = max_associativity;
        }
    }

    set_size = total_cache_size / associativity;
    number_of_lines_in_set = set_size / cache_line_size;

    offset_size = log2(cache_line_size);
    index_size = log2(number_of_lines_in_set);
    tag_size = address_size - index_size - offsetSize;

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