无法获取makefile以从其相应源构建每个对象 [英] Cannot get makefile to build each object from its corresponding source

问题描述

我对此Makefile有问题.我无法弄清楚如何从其核心响应源构建目标文件.每个obj都是使用主要来源构建的，而不是主要来源.

I am having an issue with this makefile. I cannot figure out how to build the object files from their coresponding sources. Every obj gets built with the main source, instead of its one.

TARGET   = af_optional

SOURCES := $(wildcard src/*.cpp)
OBJECTS := $(patsubst src/%.cpp,obj/%.o,$(SOURCES))
DEPENDS := $(patsubst src/%.cpp,obj/%.d,$(SOURCES))

CXXFLAGS = -g -I.

# ADD MORE WARNINGS!
WARNING := -Wall -Wextra

# .PHONY means these rules get executed even if
# files of those names exist.
.PHONY: all clean

# The first rule is the default, ie. "make",
# "make all" and "make parking" mean the same
all: bin/$(TARGET)

clean:
    $(RM) $(OBJECTS) $(DEPENDS) $(TARGET)

# Linking the executable from the object files
bin/$(TARGET): $(OBJECTS)
    @echo "target : $(TARGET)"
    @echo "sources: $(SOURCES)"
    @echo "objects: $(OBJECTS)"
    @echo "depends: $(DEPENDS)"
    @mkdir -p bin
    $(CXX) $(WARNING) $(CXXFLAGS) $^ -o $@

-include $(DEPENDS)

$(OBJECTS): $(SOURCES) makefile
    @mkdir -p obj
    $(CXX) $(WARNING) $(CXXFLAGS) -MMD -MP -c $< -o $@

我在研究时写了这个makefile，但是在使它起作用之后我弄坏了一些东西，直到现在我才注意到，因为从那以后我一直要处理的所有项目都是单一来源./p>

I have written this makefile while researching a while ago, but I broke something after I had got it working and I haven't noticed until now, since all the project's I've had to work with since were single source.

推荐答案

此规则是错误的:

$(OBJECTS): $(SOURCES) makefile

这将扩展为什么?如果您有来源 src/foo.cpp ， src/bar.cpp 和 src/baz.cpp ，那么它将是:

What does this expand to? If you have sources src/foo.cpp, src/bar.cpp, and src/baz.cpp then it will be this:

obj/foo.o obj/bar.o obj/baz.o : src/foo.cpp src/bar.cpp src/baz.cpp makefile

这是一个非常普遍的问题:人们似乎有一个想法，make将以某种方式按摩所有这些目标和先决条件以某种方式匹配它们，以便每个目标文件仅依赖于相应的源文件.

This is an extremely common problem: people seem to have this idea that make will somehow massage all these targets and prerequisites to match them up somehow so that each object file depends only on the corresponding source file.

但是，make不会那样做.上面的规则与编写所有这些规则完全相同:

But, make does NOT do that. The above rule is exactly identical to writing all these rules:

obj/foo.o : src/foo.cpp src/bar.cpp src/baz.cpp makefile
obj/bar.o : src/foo.cpp src/bar.cpp src/baz.cpp makefile
obj/baz.o : src/foo.cpp src/bar.cpp src/baz.cpp makefile

现在也许您可以看到为什么会看到自己的行为:每个目标的第一个前提条件是完全相同的文件 src/foo.cpp ，因此，当您使用 $<自动变量，这就是您总是得到的.

Now maybe you can see why you see the behavior you do: the first prerequisite for every target is exactly the same file src/foo.cpp so when you use the $< automatic variable, that's the one you always get.

您必须编写一个构建一个对象的规则，然后让我们弄清楚如何将该规则应用于所有适当的对象.

You have to write ONE rule that builds ONE object, then let make figure out how to apply that rule for all the appropriate objects.

因此，要从一个源文件构建一个目标文件，可以使用如下模式规则:

So, to build one object file from one source file you can use a pattern rule like this:

obj/%.o : src/%.cpp makefile
        @mkdir -p obj
        $(CXX) $(WARNING) $(CXXFLAGS) -MMD -MP -c $< -o $@

这就是您所需要的.

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