段寄存器如何参与存储器地址转换? [英] How are segment registers involved in memory address translation?

问题描述

到目前为止，我对细分的了解是

In what I've learned so far about segmentation:

• 虚拟地址包含一个段选择器和一个偏移量
• 分段选择器与GDTR结合使用以查找分段描述符的线性地址
• 段描述符存储有关所选段的信息，包括其线性地址

所以，我的问题是:

• 根据我所读的内容，将虚拟地址加载到段寄存器中，然后以某种方式从那里继续翻译.在将虚拟地址加载到段寄存器以获得描述符之后，段寄存器会发生什么?

• Based on what I've read, the virtual address is loaded into the segment register, and then somehow the translation is continued from there. What happens to the segment register after the virtual address has been loaded into it to obtain the descriptor?

据我了解，段寄存器还保存描述符的缓存值.在翻译过程中如何发挥作用?

As I understand it, the segment register also holds a cached value of the descriptor. How does this come into play during the translation process?

在段选择器最多可以有2 ^ 13个不同的值且只有六个主寄存器的情况下，系统如何确定要加载到哪个段寄存器?

How does the system determine which segment register to load in, given that a segment selector can have up to 2^13 different values and there are only six primary registers?

推荐答案

通常的翻译如下:

 Logical address   -->   GDT -->  Linear address          --> Page tables --> Physical Address
(segment:offset)                 (segment base + offset)         

\______________________________________________________/ 
                  Virtual address                                     
             (can be either logical or linear)

如果以VMX非根模式(即在VM中)运行并且启用了EPT，则:

If running in VMX non-root mode (i.e. in a VM) and EPT is enabled then:

 Logical address   -->   GDT -->  Linear address          --> Page tables --> Guest Physical Address --> EPT --> (System) Physical Address
(segment:offset)                 (segment base + offset)         

\______________________________________________________/                      \__________________________________________________________/
                  Virtual address                                                        Physical address
             (can be either logical or linear)

如果存在IOMMU(例如伞形技术VT-d):

If an IOMMU is present (like the umbrella technology VT-d):

Logical address   -->   GDT -->  Linear address          --> Page tables --> Guest Physical Address --> EPT --> (System) Physical Address  -->  1 or 2 level translation --> (IO) Physical address
(segment:offset)                 (segment base + offset)         

\______________________________________________________/                     \___________________________________________________________________________________________________________________/
                  Virtual address                                                        Physical address
             (can be either logical or linear)

MMIO甚至可以执行来宾虚拟地址或来宾物理地址的转换(目的之一是将应用程序的虚拟地址验证为硬件，并简化管理过程中遇到的过多地址空间的管理)翻译).

The MMIO can even perform the translation of the Guest Virtual Address or the Guest Physical Address (one of it's purposes is to reify the Virtual address of an application to the hardware and simplify the management of the plethora of address spaces encountered during the translation).

注意正如 Hadi Brais 所指出的那样，术语虚拟地址"仅在Intel和AMD手册中指定线性地址.
我发现将逻辑地址和线性地址都标记为虚拟地址更为有用，因为它们在页面转换步骤之前.

Note As Hadi Brais pointed out, the term "Virtual address" only designates a Linear address in the Intel and AMD manuals.
I find it more useful to label both the logical and the linear addresses as virtual because they are before the page translation step.

段寄存器包含一个段选择器，该段索引一个段描述符，该段用于执行安全检查并获取段 base 与逻辑地址的偏移量部分相加.
之后，就完成了.

The segment register holds a segment selector that index a segment descriptor that is used to performs the security checks and get the segment base that is summed with the offset part of the logical address.
After that, it's done.

在指令级别指定的每个地址都是逻辑地址-需要查找段 descriptor .
为了避免每次通过指令访问内存时从内存中读取内存，CPU会将其缓存-否则会导致性能下降.

Every address specified at the instruction level is a logical address - requiring the lookup of the segment descriptor.
To avoid reading it from memory each time the memory is accessed by an instruction, the CPU caches it - otherwise that would be a performance killer.

操作系统根据需要执行的操作来设置段寄存器，但是无论如何它很少需要四个以上的段.

The OS setup the segment registers based on what it need to do but it rarely need more that four segments anyway.

分段的主要目的(在PM中)是通过为每个程序定义不重叠的分段来实现进程隔离.
程序通常只需要一个堆栈段，一个数据段和一个代码段-其他三个段在那里以避免在段最大大小为64KiB时保存/恢复数据段(读取:实模式. fs 和 gs 稍后添加).

The primary intent for segmentation (in PM) was to fulfil process isolation by defining non overlapping segments for each program.
A program usually need only a stack segment, a data segment and a code segment - the other three are there to avoid saving/restoring the data segment back then when a segment max size was 64KiB (read: Real mode. fs and gs were added later though).

当今的OS使用平面模型，其中只有两个段(代码和数据/堆栈-这是一个简化，需要其他段)涵盖整个地址空间，另外还包括TLS或PEB/TEB之类的OS特定段.
因此，六个段寄存器甚至比需要的还要多.如果需要(即使是偶数)，则GDT的8192个条目就会存在.

Today OSes use a flat model where there are only two segments (code and data/stack - this is a simplification, other segments are required) encompassing the whole address space, plus OS specifics segments for things like TLS or PEB/TEB.
So six segment registers are even more than it's needed, the 8192 entries of the GDT are there in case they are (if even) needed.

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