DMA控制器如何处理输入设备(例如串行端口) [英] How DMA Controller handles the Input devices like say Serial port

问题描述

因此，到目前为止，我了解到的是，只要需要从硬盘驱动器传输数据，CPU就会对源地址，目标地址，字数和到DMA控制器的方向进行编程.但是在此示例中，硬盘驱动器只是一个哑设备，因此很有意义，因为硬盘驱动器永远无法启动数据传输.

但是，如果我们连接了串行端口，那么在某些情况下我们将获得8位数据该怎么办.我知道DMA控制器用于大内存传输，但是我想对这8位进行DMA.但是，CPU上的设备驱动程序无法确定什么时候有数据进来，也无法知道有多少数据要进来，因为串行端口可能发送8位或16位或根本没有数据.因此，在这种情况下，谁来填充DMA控制器的计数和内存地址，因为当要输入数据时，设备驱动程序是完全未知的.

当传入的数据不是连续流或固定长度的数据包时，使用DMA串行 input 会很复杂.确切的细节将取决于特定的UART和DMA控制器，但是通常，到达的每个字符都将被复制到提供的DMA缓冲区中的 next 位置，并且DMA控制器将产生一个中断当缓冲区同时填充一半和完全填充时.

与使用UART的数据可用中断相比，单字节DMA缓冲区的作用不大，只会将字节处理延迟一个字符周期.

如果您的DMA缓冲区有两个字符长，那么您将得到一个每个字符的中断(一个用于半传输，一个用于全传输)，这解决了部分中断的问题.填充缓冲区不被服务，但是根本不减少中断开销，因此与直接UART中断处理相比，优势不大.如果您的UART包含FIFO缓冲区，那么在仅需要少量缓冲的情况下，这将是处理异步串行输入的更好方法.

使用较大的DMA缓冲区时，中断速率会降低，但是当缓冲区不完整时，您不会收到中断，并且数据可能会无限期等待.解决该问题的一种方法是实施超时机制，如果DMA中断在由波特率和缓冲区长度确定的时间段内未到达，则超时处理程序将检索当前缓冲的所有数据.这种机制需要注意避免超时和DMA中断之间的争用情况，并确保在处理超时时 到达的数据不会丢失，或者不会重复通过超时获取的数据当DMA中断最终到达时.

So, what I have learned so far is that CPU programs the source address, dest address, word count and the direction to the DMA controller whenever it needs to transfer the data from say a harddrive. But in this example, the hard drive is just a dumb device, so it makes sense because harddrive can never initiate a data transfer.

But, what if we have connected the serial port where in certain instances we are going to get 8 bits of data. I know the DMA controller is used for large memory transfer, but say I want to do DMA for these 8 bits. But the device driver on the CPU cannot tell when the data is coming and it also can not tell how much data is coming because the serial port may send 8 bits or 16 bits or no data at all. So in this case who fills the DMA controller's count and memory addresses since the device driver is completely unknown when the data is going to come in.

解决方案

Using DMA serial input is complicated when the incoming data is not a continuous stream or fixed length packets. The exact details will depend on the specific UART and DMA controller, but generally, each character that arrives will be copied to the next location in the provided DMA buffer, and an interrupt will be generated by the DMA controller when the buffer is both half-filled and completely filled.

A single byte DMA buffer serves little purpose over using the UART's data avalable interrupt, and will simply delay byte processing by one character period.

If your DMA buffer were two characters long, you'd then get an interrupt for every character (one for the half transfer, and one for the full transfer), which solves the problem of partially filled buffers not being serviced, but does not reduce the interrupt overhead at all so offers little advantage over direct UART interrupt handling. If your UART includes a FIFO buffer, that would be a better method of dealing with asynchronous serial input when only a small amount of buffering is required.

When a larger DMA buffer is used the interrupt rate is reduced, but when a buffer is incomplete you will not get an interrupt, and the data may wait indefinitely. One solution to that problem is to implement a timeout mechanism whereby if the DMA interrupt does not arrive within a time period determined by the baud rate and buffer length, then the timeout handler retrieves all data currently buffered. Such a mechanism requires care to avoid race conditions between the timeout and the DMA interrupt, and to ensure that data arriving while the timeout is being processed is not lost, or that data retrieved by the timeout is not repeated when the DMA interrupt eventually arrives.

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