VHDL缓冲区变量vs输出变量 [英] VHDL buffer variable vs out variable

问题描述

我在VHDL程序中工作，我需要使用ALTERA DE2-115做RAM 256.输出将显示在七段显示中.问题是:我有一个 dataout 输出变量.然后，变量具有 temp_ram 数组的以下值:

I work in a VHDL program and I need to do a RAM 256 using the ALTERA DE2-115. The outputs will show in a seven segment display. The problem is that: I have a dataout output variable. Then the variable has the following values of the temp_ram array:

dataout <= temp_ram(conv_integer(dir));

然后我想将 dataout 的值划分为七个部分

Then I want to divide the vaules of dataout to put in the seven segment

dataout(7 downto 4)
dataout(3 downto 0)

这将显示以下错误:

Error (10309): VHDL Interface Declaration error in RAM.vhd(45): interface object "dataout" of mode out cannot be read. Change object mode to buffer.

当我更改为buffer并且运行时，但是我不知道会发生什么

When I change to buffer and this run prefect, but I can't understand what happen

推荐答案

为实现跨平台兼容性和代码可重用性，我建议使用中间信号(dataout_int可以由其他语句使用):

For cross-platform compatibility and code-reusability, I'd recommend an intermediate signal ( dataout_int can be used by other statements) :

    dataout_int <= temp_ram(conv_integer(dir));

并将输出分配给该中间信号:

and assign the output to this intermediate signal:

    dataout <= dataout_int;

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