从Makefile中的目标名称中提取宏参数 [英] Extract macro parameters from target name in Makefile

问题描述

我的makefile中有很多这样的行，但排列不同.我想使用一般规则来自动化它们，因此，如果键入 $ make foo-WHATEVER ，make会知道如何从 foo.c 和相关的-D标志构建它.

I have a bunch of lines like this in my makefile, in different permutations. I want to automate them with a general rule, so if I type $ make foo-WHATEVER, make knows how to build it from foo.c and relevant -D flags.

foo-PARAMA.o: foo.c
foo-PARAMA.o: CPPFLAGS += -DPARAMA

foo-PARAMA-PARAMB.o: foo.c
foo-PARAMA-PARAMB.o: CPPFLAGS += -DPARAMA -DPARAMB

foo-PARAMA-PARAMB-PARAMC.o: foo.c
foo-PARAMA-PARAMB-PARAMC.o: CPPFLAGS += -DPARAMA -DPARAMB -DPARAMC

推荐答案

好吧，您可以尝试执行以下操作:

Well, you can try something like this:

foo-%.o : foo.c
        $(CC) $(CPPFLAGS) $(addprefix -D,$(subst -, ,$*)) $(CFLAGS) -o $@ -c $<

但是我怀疑您真的想对任何源文件"执行此操作，而不仅仅是 foo.c .这要困难得多，因为您不能在单个目标或先决条件中拥有多个模式.

but my suspicion is that you're really going to want to do this for "any source file" not just foo.c. That's much harder because you can't have multiple patterns in a single target or prerequisite.

为此，您必须预先知道源文件列表，并使用 eval :

For that you'll have to know the list of source files up-front and use eval:

SRCS = foo.c bar.c baz.c biz.c

define make-pattern
$1-%.o : $1.c
        $$(CC) $$(CPPFLAGS) $$(addprefix -D,$$(subst -, ,$$*)) $$(CFLAGS) -o $$@ -c $$<
endif

$(foreach S,$(SRCS),$(eval $(call make-pattern,$S)))

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