我如何体验"LFENCE或SFENCE无法通过较早的读/写"? [英] How can I experience "LFENCE or SFENCE can not pass earlier read/write"
问题描述
我正在做一些关于功能安全性的事情.我需要验证一些X86 CPU指令，例如LFENCE，SFENCE和MFENCE.
I'm doing something about function safety. I need verify some X86 CPU instructions, such as LFENCE, SFENCE and MFENCE.
现在，根据英特尔SDM第8.2.3.4节可以通过较早的存储将负载重新排序到其他位置，"我可以体验MFENCE.
Now I can experience MFENCE according to Intel SDM chapter 8.2.3.4 "loads may be reordered with earlier store to different location".
"xor %0, %0\n\t "
"movl $1, %1\n\t "
"mfence\n\t "
"movl %2, %0\n\t "
: "=r"(r1), "=m" (X)
: "m"(Y)
: "memory");
"xor %0, %0\n\t "
"movl $1, %1\n\t "
"mfence\n\t "
"movl %2, %0\n\t "
: "=r"(r2), "=m" (Y)
: "m"(X)
: "memory");
仅在以上代码中体验MFENCE可以防止内存重新排序(通过在两个处理器中删除mfence之前/之后检测r1和r2的不同值)
Above code only experience MFENCE could prevent memory reordering.(by detect the different value of r1 and r2 before/after removing mfence in both processors)
所以我想知道如何像上面那样验证LFENCE和SFENCE.我在SDM中找不到任何逻辑.
So I'm wondering how can I verify LFENCE and SFENCE like above. I didn't find any logic in SDM.
推荐答案
sfence has no real effect unless you're using NT stores1. If you NT-store data and then a pointer to that data (or a "ready" flag), a reader can see the old value for the data even if they see the new pointer / flag value. sfence can be used to ensure that the two stores become observable in program order.
lfence 对于内存排序是无用的.创建一个案例很难，要注释掉它会在内存排序中创建一个可检测的不同 .
lfence is useless for memory ordering unless you're doing NT loads from a WC memory region (like video RAM). You'll have a very hard time creating a case where commenting it out creates a detectable different in memory ordering.
lfence 的主要用途是序列化执行，而不是内存.参见了解影响在具有两个长依赖性链的循环上的长度增加长度
The main use for lfence is to serialize execution, not memory. See Understanding the impact of lfence on a loop with two long dependency chains, for increasing lengths
由于您不仅询问C语言，而且还询问了何时应使用 _mm_sfence()和其他 intrinsics .何时应使用_mm_sfence _mm_lfence和_mm_mfence (通常，您实际上只需要 asm(" :::"memory"); 除非有NT存储处于运行状态，否则由于编译时重新排序会给您带来acq/rel排序没有任何运行时障碍说明.)
Since you asked about C not just asm, there's a related answer about when you should use _mm_sfence() and other intrinsics. When should I use _mm_sfence _mm_lfence and _mm_mfence (usually you really only need asm("" ::: "memory"); unless NT stores are in flight, because blocking compile-time reordering gives you acq / rel ordering without any runtime barrier instructions.)
脚注1:对于普通的WB(WriteBack)而言，这是正确的.在普通操作系统下的用户空间中，除非您做了一些非常特殊的操作，否则这就是您一直拥有的.
Footnote 1: That's true for normal WB (WriteBack) memory cacheability settings. In user-space under a normal OS, that's what you always have unless you did something very special.
对于其他内存类型(MTRR或PAT设置):不可缓存内存上的NT存储没有特殊作用，并且仍然是有序的.在WC，WB或WT内存上的NT存储(或到WC内存的普通存储)的排序很弱，因此在为另一个线程存储 buffer_ready 标志之前使用 sfence 很有用
For other memory types (MTRR or PAT settings): NT stores on uncacheable memory have no special effect, and are still strongly ordered. NT stores on WC, WB, or WT memory (or normal stores to WC memory) are weakly ordered and make it useful to use sfence before storing a buffer_ready flag for another thread.
SSE4.1 movntdqa 加载的排序不严格.与商店不同，它不会覆盖内存类型的排序语义.在当前的CPU上，WB存储器上没有什么特别的事情发生.它们只是效率较低的 movdqa 包la.只能在WC内存上使用它们.
SSE4.1 movntdqa loads from WB memory are not weakly ordered. Unlike stores, it doesn't override the memory type's ordering semantics. On current CPUs, nothing special happens at all on WB memory; they're just a less-efficient movdqa laod. Only use them on WC memory.
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