如何将Intel TSX与C ++内存模型一起使用? [英] How to use Intel TSX with C++ memory model?

问题描述

我认为C ++尚未涵盖任何类型的事务内存，但是TSX仍可以使用"仿佛规则"以某种方式适合由C ++内存模型控制的事物.

I think C++ does not cover any sort of transaction memory yet, but still TSX can somehow fit using "as if rule" into something that is governed by C++ memory model.

那么，成功的HLE操作或成功的RTM事务会发生什么?

So, what happens on successful HLE operation, or successful RTM transaction?

说有数据竞赛，但没关系"并没有多大帮助，因为它并不清楚"ok"的含义.

Saying "there is data race, but it is ok" is not much helpful, as it does not clarify what "ok" means.

对于HLE，可能将其视为先前的操作发生在后续的操作之前.好像该节仍由被消除的锁保护着."

With HLE probably it can be seen as "previous operation happens before subsequent operation. As if the section was still guarded by the lock that was elided".

RTM是什么?由于甚至没有消除的锁，因此只有(可能是非原子的)内存操作可以是加载，存储，两者或无操作.什么与什么同步?在发生什么之前会发生什么?

What is with RTM? As there's no even an elided lock, only (potentially non-atomic) memory operations, which could be loads, stores, both, or no-op. What is synchronized with what? What happens before what?

推荐答案

显然，在进入规格或要求SO之前，我应该仔细阅读概述"页面:

Apparently before going into specs or asking SO I should have read thoroughly "overview" pages:

硬件锁定清除概述

硬件确保锁上操作的程序顺序，甚至尽管淘汰处理器未执行外部写入操作锁.如果选举处理器本身读取了锁定关键部分，就好像处理器已经获取了锁(读取将返回非保留值).这行为使HLE执行在功能上等同于没有HLE前缀的执行.

The hardware ensures program order of operations on the lock, even though the eliding processor did not perform external write operations to the lock. If the eliding processor itself reads the value of the lock in the critical section, it will appear as if the processor had acquired the lock (the read will return the non-elided value). This behavior makes an HLE execution functionally equivalent to an execution without the HLE prefixes.

受限事务性内存概述

RTM内存排序

成功提交RTM会导致RTM区域中的所有内存操作似乎是原子执行的.成功提交的RTM区域由XBEGIN和XEND组成，即使没有内存也是如此RTM区域中的操作具有与LOCK前缀指令.XBEGIN指令没有围栏语义.但是，如果RTM执行中止，则所有内存RTM区域内的更新将被丢弃并且永远不会进行任何其他逻辑处理器都可以看到.

RTM Memory Ordering

A successful RTM commit causes all memory operations in the RTM region to appear to execute atomically. A successfully committed RTM region consisting of an XBEGIN followed by an XEND, even with no memory operations in the RTM region, has the same ordering semantics as a LOCK prefixed instruction. The XBEGIN instruction does not have fencing semantics. However, if an RTM execution aborts, all memory updates from within the RTM region are discarded and never made visible to any other logical processor.

要完成答案:

LOCK 前缀指令映射到C ++ std :: memory_order :: seq_cst .这涵盖了所有成功的RTM事务(就像单个 LOCK 前缀指令一样).它还涵盖了大多数HLE案例.具体来说:

LOCK prefixed instructions map to C++ std::memory_order::seq_cst. This covers all successful RTM transactions (which are as if single LOCK-prefixed instruction). It also covers most of HLE cases. Specifically:

• LOCK 前缀指令的执行就像执行一样，这也意味着 seq_cst
• XACQUIRE XCHG / XRELEASE XCHG 相同，就好像它已执行一样，这也暗示了 seq_cst
• 最后， XRELEASE MOV [mem]，op 就像 MOV [mem]，op 一样，所以它只是 release (在C ++内存模型的通常实现，其中顺序一致的存储具有内存隔离，而不是加载)

• LOCK prefixed instructions are executed as if they are executed, this implies seq_cst too
• The same for XACQUIRE XCHG / XRELEASE XCHG, as if it is executed, this implies seq_cst too
• Finally, XRELEASE MOV [mem], op is as if MOV [mem], op, so it is just release (under usual implementation of C++ memory model where sequentially consistent store has memory fence, not load)

(文档链接适用于Intel编译器.但是它们记录了硬件行为，因此该信息应适用于其他编译器.编译器可能会引入的唯一变量是编译时间重新排序.但是，我希望如果编译器实现内在函数，它将还执行适当的重新排序禁止，如果仍然不确定，请放置编译器障碍.对于直接汇编，应仅在汇编代码中进行相应的标记)

(The documentation links are for Intel compiler. However they document hardware behavior, so the information should be applicable to other compilers. The only variable that compiler might introduce is compile time reordering. I expect however that if compiler implements intrinsic, it also implements proper reordering prohibition, if still unsure, place compiler barriers. And with direct assembly should just mark assembly code accordingly)

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