可以使undefine一个变量吗? [英] Can Make undefine a variable?

问题描述

我在嵌入式系统(RTXC)中工作，需要禁用通过#define命令启用的调试器功能.但是，当我将#define更改为undefine时，编译会正常进行，但是当链接程序运行时，它会遇到有关不属于调试代码的符号的错误(调试器变量应注意该错误)正在定义).Make有什么方法可以确保预处理器变量未定义或保持未定义状态?

解决方案

您的问题的答案是否定的，Make不能完全阻止变量由例如代码中的#define表达式定义.

您似乎有一个难以捉摸的问题.可能是Makefile中的错误，指令拼写错误，宏错误(如果您愿意重言重述)或琐碎的事情.我建议燃烧森林:砍掉一切，直到问题解决为止，然后查看它的藏身之处.如果您进入HelloWorld并且问题仍然存在，请告诉我们.

I'm working in an embedded system (RTXC) where I need to disable the debugger functionality which is enabled through a #define command. However, when I change the #define to undefine, compilation goes off fine, but when the linker runs, it encounters an error about a symbol not existing that belongs to the debug code (which should have been taken care of by the debugger variable not being defined). Is there any way for Make to ensure that a preprocessor variable does not get defined or stays undefined ?

解决方案

The answer to your question is no, Make can't absolutely prevent a variable from being defined by, say, a #define expression in the code.

You seem to have an elusive problem. It could be a bug in your Makefiles, a misspelled directive, a bad macro (if you'll pardon the tautology) or something trivial. I'd suggest burning the forest: cut out everything until the problem stops, then see where it was hiding. If you get down to HelloWorld and the problem persists, let us know.

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