Makefile编译源文件列表 [英] Makefile to compile lists of source files

问题描述

我有一些要让我的Makefile编译的文件列表，每种源语言都有一个列表:

I have lists of files that I want my Makefile to compile, one list for each source language:

CFILES=  Src/Application/main.c  Src/Core/data.c  Lib/routines.c
ASFILES= Src/Application/startup.s  Lib/sqrt.s

我希望所有输出都在一个目录中:

I want all the output in one directory:

OBJDIR= output

我该如何做:

output/main.o     : Src/Application/main.c
    cc -c -o output/main.o Src/Application/main.c

output/data.o     : Src/Core/data.c
    cc -c -o output/data.o Src/Core/data.c

output/routines.o : Lib/routines.c
    cc -c -o output/routines.o Lib/routines.c

output/startup.o  : Src/Application/startup.s
    as -o output/startup.o Src/Application/startup.s

output/sqrt.o     : Lib/sqrt.s
    as -o output/sqrt.o  Lib/sqrt.s

列表中每个文件的配方都是相同的.

The recipes are the same for every file in its list.

输入文件位于各种不同的目录中，仅列出其文件名并使用搜索路径来查找它们是不可接受的，必须使用其显式路径.

The input files are in all sorts of different directories and it is not acceptable to just list their filenames and use a search path to find them, their explicit paths must be used.

输出文件名是源文件名的基本名称，扩展名更改为o.列表之间没有针对不同源语言的重复基名.

The output filename is the basename of the source file name with the extension changed to o. There are no duplicated basenames between the lists for the different source languages.

我不想列出目标文件，这应该从源列表中导出.

I do not want to have to list the object files, this should be derived from the source lists.

我正在使用gnu make，但是可移植解决方案的奖励积分.

I am using gnu make, but bonus points for a portable solution.

推荐答案

可以执行以下操作:

all :

OBJDIR := output
CFILES  := Src/Application/main.c Src/Core/data.c Lib/routines.c
ASFILES := Src/Application/startup.s Lib/sqrt.s

target = ${OBJDIR}/$(patsubst %.s,%.o,$(notdir ${1}))
obj.c :=
obj.s :=
define obj
  $(call target,${1}) : ${1} | ${OBJDIR}
  obj$(suffix ${1}) += $(call target,${1})
  ${1} : ; mkdir -p `dirname $$@` && touch $$@ # Create the source for testing. Remove this.
endef

define SOURCES
  $(foreach src,${1},$(eval $(call obj,${src})))
endef

$(eval $(call SOURCES,${CFILES}))
$(eval $(call SOURCES,${ASFILES}))

all : ${obj.c} ${obj.s}

${obj.c} : % :
    @echo cc -c -o $@ $^; touch $@ # echo and touch are for testing. Remove these.

${obj.s} : % :
    @echo as -o $@ $^; touch $@ # echo and touch are for testing. Remove these.

${OBJDIR} :
    mkdir $@

.PHONY: all

输出:

$ make 
make: Entering directory '/home/max/tmp'
mkdir -p `dirname Src/Application/main.c` && touch Src/Application/main.c # Create the source for testing. Remove this.
mkdir output
cc -c -o output/main.c Src/Application/main.c
mkdir -p `dirname Src/Core/data.c` && touch Src/Core/data.c # Create the source for testing. Remove this.
cc -c -o output/data.c Src/Core/data.c
mkdir -p `dirname Lib/routines.c` && touch Lib/routines.c # Create the source for testing. Remove this.
cc -c -o output/routines.c Lib/routines.c
mkdir -p `dirname Src/Application/startup.s` && touch Src/Application/startup.s # Create the source for testing. Remove this.
as -o output/startup.o Src/Application/startup.s
mkdir -p `dirname Lib/sqrt.s` && touch Lib/sqrt.s # Create the source for testing. Remove this.
as -o output/sqrt.o Lib/sqrt.s
make: Leaving directory '/home/max/tmp'

这篇关于Makefile编译源文件列表的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！