如何明确并从用户模式在Linux 2.6.35无效ARM V7处理器缓存 [英] How clear and invalidate ARM v7 processor cache from User Mode on Linux 2.6.35

问题描述

我想清楚，为无效指令行ARM V7处理器缓存，因为指令codeS可以执行更改。

I tried clear and invalidate ARM v7 processor cache for instruction line, because instruction codes can change in execution.

有关深远的影响，我试过2变种。在这里，他们是：

For reaching the effect, I tried 2 variants. Here they are:

1. 我用GCC的 __ clear_cache（）的功能，但它并没有给出所需的结果。指令codeS在缓存中没有改变。

1. I used GCC __clear_cache() function but it didn't give a required result. Instruction codes in cache didn't change.

我找了一个源$ C ​​$ CS GCC和发现的的uClinux-eabi.h文件，我发现下一个code清除缓存：

I looked for a source codes for GCC and found the uclinux-eabi.h file where I found the next code for clearing cache:

/* Clear the instruction cache from `beg' to `end'.  This makes an
   inline system call to SYS_cacheflush.  */
#undef CLEAR_INSN_CACHE
#define CLEAR_INSN_CACHE(BEG, END)                                    \
{                                                                     \
    register unsigned long _beg __asm ("a1") = (unsigned long) (BEG); \
    register unsigned long _end __asm ("a2") = (unsigned long) (END); \
    register unsigned long _flg __asm ("a3") = 0;                     \
    register unsigned long _scno __asm ("r7") = 0xf0002;              \
    __asm __volatile                                                  \
    (                                                                 \
        "swi 0x0    @ sys_cacheflush"                                 \
        : "=r" (_beg)                                                 \
        : "0" (_beg), "r" (_end), "r" (_flg), "r" (_scno));           \
}

该变种没有给结果了。

也许有人知道我做错了什么？

Maybe someone knows what I do wrong ?

推荐答案

我有一个类似的问题我自己。 __clear_cache（）的工作，但仅当所讨论的存储区域，使用与PROT_EXEC集MMAP（）分配的。如果你为它提供来自普通的malloc（）的内存的内存范围的Linux将不刷新指令缓存，即使处理器似乎很乐​​意通过malloc（）的内存执行code。

I had a similar problem myself. __clear_cache() works, but only if the memory area in question was allocated using mmap() with PROT_EXEC set. Linux will not flush the instruction cache if you provide it with a memory range that comes from regular malloc()ed memory, even if the processor seems to be happy to execute code from malloc()ed memory.

请参阅的https://community.arm.com/groups/processors/blog/2010/02/17/caches-and-self-modifying-$c$c有关如何做到这一点的例子code。

See https://community.arm.com/groups/processors/blog/2010/02/17/caches-and-self-modifying-code for example code on how to do this.

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